src/HOL/TLA/Memory/Memory.ML
author wenzelm
Thu Mar 11 13:20:35 1999 +0100 (1999-03-11)
changeset 6349 f7750d816c21
parent 6255 db63752140c7
child 7881 1b1db39a110b
permissions -rw-r--r--
removed foo_build_completed -- now handled by session management (via usedir);
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(* 
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    File:        Memory.ML
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    Author:      Stephan Merz
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    Copyright:   1997 University of Munich
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    RPC-Memory example: Memory specification (theorems and proofs)
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*)
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val RM_action_defs = 
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   [MInit_def, PInit_def, RdRequest_def, WrRequest_def, MemInv_def,
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    GoodRead_def, BadRead_def, ReadInner_def, Read_def,
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    GoodWrite_def, BadWrite_def, WriteInner_def, Write_def,
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    MemReturn_def, RNext_def];
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val UM_action_defs = RM_action_defs @ [MemFail_def, UNext_def];
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val RM_temp_defs = [RPSpec_def, MSpec_def, IRSpec_def];
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val UM_temp_defs = [UPSpec_def, MSpec_def, IUSpec_def];
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val mem_css = (claset(), simpset());
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(* -------------------- Proofs ---------------------------------------------- *)
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(* The reliable memory is an implementation of the unreliable one *)
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qed_goal "ReliableImplementsUnReliable" Memory.thy 
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   "|- IRSpec ch mm rs --> IUSpec ch mm rs"
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   (K [force_tac (temp_css addsimps2 ([UNext_def,UPSpec_def,IUSpec_def] @ RM_temp_defs)
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			   addSEs2 [STL4E,squareE]) 1]);
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(* The memory spec implies the memory invariant *)
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qed_goal "MemoryInvariant" Memory.thy 
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   "|- MSpec ch mm rs l --> [](MemInv mm l)"
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   (fn _ => [ auto_inv_tac (simpset() addsimps RM_temp_defs @ RM_action_defs) 1 ]);
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(* The invariant is trivial for non-locations *)
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qed_goal "NonMemLocInvariant" Memory.thy
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   "|- #l ~: #MemLoc --> [](MemInv mm l)"
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   (K [ auto_tac (temp_css addsimps2 [MemInv_def] addSIs2 [necT]) ]);
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qed_goal "MemoryInvariantAll" Memory.thy
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   "|- (!l. #l : #MemLoc --> MSpec ch mm rs l) --> (!l. [](MemInv mm l))"
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    (K [step_tac temp_cs 1,
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	case_tac "l : MemLoc" 1,
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	auto_tac (temp_css addSEs2 [MemoryInvariant,NonMemLocInvariant]) ]);
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(* The memory engages in an action for process p only if there is an 
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   unanswered call from p.
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   We need this only for the reliable memory.
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*)
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qed_goal "Memoryidle" Memory.thy
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   "|- ~$(Calling ch p) --> ~ RNext ch mm rs p"
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   (K [ auto_tac (mem_css addsimps2 (Return_def::RM_action_defs)) ]);
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(* Enabledness conditions *)
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qed_goal "MemReturn_change" Memory.thy
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   "|- MemReturn ch rs p --> <MemReturn ch rs p>_(rtrner ch ! p, rs!p)"
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   (K [ force_tac (mem_css addsimps2 [MemReturn_def,angle_def]) 1]);
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qed_goal "MemReturn_enabled" Memory.thy
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   "!!p. basevars (rtrner ch ! p, rs!p) ==> \
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\        |- Calling ch p & (rs!p ~= #NotAResult) \
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\           --> Enabled (<MemReturn ch rs p>_(rtrner ch ! p, rs!p))"
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  (K [action_simp_tac (simpset()) [MemReturn_change RSN (2,enabled_mono)] [] 1,
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      action_simp_tac (simpset() addsimps [MemReturn_def,Return_def,rtrner_def])
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                             [] [base_enabled,Pair_inject] 1
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	    ]);
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qed_goal "ReadInner_enabled" Memory.thy
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 "!!p. basevars (rtrner ch ! p, rs!p) ==> \
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\      |- Calling ch p & (arg<ch!p> = #(read l)) --> Enabled (ReadInner ch mm rs p l)"
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   (fn _ => [case_tac "l : MemLoc" 1,
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             ALLGOALS
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	        (action_simp_tac 
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                    (simpset() addsimps [ReadInner_def,GoodRead_def,BadRead_def,
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					RdRequest_def])
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                    [] [base_enabled,Pair_inject])
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            ]);
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qed_goal "WriteInner_enabled" Memory.thy
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   "!!p. basevars (mm!l, rtrner ch ! p, rs!p) ==> \
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\        |- Calling ch p & (arg<ch!p> = #(write l v)) \
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\           --> Enabled (WriteInner ch mm rs p l v)"
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   (fn _ => [case_tac "l:MemLoc & v:MemVal" 1,
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             ALLGOALS (action_simp_tac 
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                 (simpset() addsimps [WriteInner_def,GoodWrite_def,BadWrite_def,
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					WrRequest_def] delsimps [disj_not1])
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                    [] [base_enabled,Pair_inject])
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            ]);
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qed_goal "ReadResult" Memory.thy
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   "|- Read ch mm rs p & (!l. $(MemInv mm l)) --> (rs!p)` ~= #NotAResult"
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   (fn _ => [force_tac (mem_css addsimps2 
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                            [Read_def,ReadInner_def,GoodRead_def,BadRead_def,MemInv_def]) 1]);
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qed_goal "WriteResult" Memory.thy
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   "|- Write ch mm rs p l --> (rs!p)` ~= #NotAResult"
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   (fn _ => [auto_tac (mem_css addsimps2 ([Write_def,WriteInner_def,GoodWrite_def,BadWrite_def]))
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	    ]);
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qed_goal "ReturnNotReadWrite" Memory.thy
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   "|- (!l. $MemInv mm l) & MemReturn ch rs p \
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\      --> ~ Read ch mm rs p & (!l. ~ Write ch mm rs p l)"
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   (fn _ => [auto_tac
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	       (mem_css addsimps2 [MemReturn_def] addSDs2 [WriteResult, ReadResult])
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	    ]);
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qed_goal "RWRNext_enabled" Memory.thy
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   "|- (rs!p = #NotAResult) & (!l. MemInv mm l)  \
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\          & Enabled (Read ch mm rs p | (? l. Write ch mm rs p l)) \
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\      --> Enabled (<RNext ch mm rs p>_(rtrner ch ! p, rs!p))"
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   (K [force_tac (mem_css addsimps2 [RNext_def,angle_def]
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	     addSEs2 [enabled_mono2]
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	     addDs2 [ReadResult, WriteResult]) 1]);
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(* Combine previous lemmas: the memory can make a visible step if there is an
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   outstanding call for which no result has been produced.
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*)
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qed_goal "RNext_enabled" Memory.thy
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"!!p. !l. basevars (mm!l, rtrner ch!p, rs!p) ==> \
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\     |- (rs!p = #NotAResult) & Calling ch p & (!l. MemInv mm l)  \
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\        --> Enabled (<RNext ch mm rs p>_(rtrner ch ! p, rs!p))" (K [
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	     auto_tac (mem_css addsimps2 [enabled_disj]
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		                  addSIs2 [RWRNext_enabled]),
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             exhaust_tac "arg(ch w p)" 1,
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 	      action_simp_tac (simpset()addsimps[Read_def,enabled_ex])
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	                      [ReadInner_enabled,exI] [] 1,
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              force_tac (mem_css addDs2 [base_pair]) 1,
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	     etac swap 1,
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	     action_simp_tac (simpset() addsimps [Write_def,enabled_ex])
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	                     [WriteInner_enabled,exI] [] 1]);
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