src/Pure/axclass.ML
changeset 14695 9c78044b99c3
parent 14605 9de4d64eee3b
child 14785 d88f4c8f0591
     1.1 --- a/src/Pure/axclass.ML	Sat May 01 22:07:16 2004 +0200
     1.2 +++ b/src/Pure/axclass.ML	Sat May 01 22:08:57 2004 +0200
     1.3 @@ -96,7 +96,7 @@
     1.4  
     1.5  fun mk_arity (t, Ss, c) =
     1.6    let
     1.7 -    val tfrees = ListPair.map TFree (Term.invent_type_names [] (length Ss), Ss);
     1.8 +    val tfrees = ListPair.map TFree (Term.invent_names [] "'a" (length Ss), Ss);
     1.9    in Logic.mk_inclass (Type (t, tfrees), c) end;
    1.10  
    1.11  fun mk_arities (t, Ss, S) = map (fn c => mk_arity (t, Ss, c)) S;