src/HOL/MicroJava/BV/BVSpecTypeSafe.thy
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(*  Title:      HOL/MicroJava/BV/BVSpecTypeSafe.thy
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    ID:         $Id$
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    Author:     Cornelia Pusch
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    Copyright   1999 Technische Universitaet Muenchen
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Proof that the specification of the bytecode verifier only admits type safe
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programs.
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*)
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header "BV Type Safety Proof"
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theory BVSpecTypeSafe = Correct:
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lemmas defs1 = sup_state_conv correct_state_def correct_frame_def 
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               wt_instr_def step_def
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lemmas widen_rules[intro] = approx_val_widen approx_loc_widen approx_stk_widen
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lemmas [simp del] = split_paired_All
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lemma wt_jvm_prog_impl_wt_instr_cor:
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  "[| wt_jvm_prog G phi; method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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      G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
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  ==> wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc"
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apply (unfold correct_state_def Let_def correct_frame_def)
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apply simp
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apply (blast intro: wt_jvm_prog_impl_wt_instr)
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done
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section {* Single Instructions *}
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lemmas [iff] = not_Err_eq
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lemma Load_correct:
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"[| wf_prog wt G;
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    method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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    ins!pc = Load idx; 
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    wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
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    Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs); 
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    G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
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==> G,phi \<turnstile>JVM state'\<surd>"
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apply (clarsimp simp add: defs1 map_eq_Cons)
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apply (blast intro: approx_loc_imp_approx_val_sup)
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done
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lemma Store_correct:
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"[| wf_prog wt G;
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  method (G,C) sig = Some (C,rT,maxs,maxl,ins);
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  ins!pc = Store idx;
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  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc;
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  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs);
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  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |]
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==> G,phi \<turnstile>JVM state'\<surd>"
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apply (clarsimp simp add: defs1 map_eq_Cons)
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apply (blast intro: approx_loc_subst)
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done
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lemma LitPush_correct:
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"[| wf_prog wt G;
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    method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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    ins!pc = LitPush v;
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    wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
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    Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs);
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    G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |]
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==> G,phi \<turnstile>JVM state'\<surd>" 
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apply (clarsimp simp add: defs1 sup_PTS_eq map_eq_Cons)
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apply (blast dest: conf_litval intro: conf_widen)
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done
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lemma Cast_conf2:
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  "[| wf_prog ok G; G,h\<turnstile>v::\<preceq>RefT rt; cast_ok G C h v; 
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      G\<turnstile>Class C\<preceq>T; is_class G C|] 
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  ==> G,h\<turnstile>v::\<preceq>T"
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apply (unfold cast_ok_def)
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apply (frule widen_Class)
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apply (elim exE disjE) 
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 apply (simp add: null)
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apply (clarsimp simp add: conf_def obj_ty_def)
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apply (cases v)
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apply (auto intro: rtrancl_trans)
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done
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lemma Checkcast_correct:
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"[| wf_prog wt G;
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    method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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    ins!pc = Checkcast D; 
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    wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
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    Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
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    G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
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==> G,phi \<turnstile>JVM state'\<surd>"
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apply (clarsimp simp add: defs1 map_eq_Cons raise_xcpt_def)
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apply (blast intro: Cast_conf2)
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done
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lemma Getfield_correct:
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"[| wf_prog wt G;
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  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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  ins!pc = Getfield F D; 
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  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
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  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
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  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
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==> G,phi \<turnstile>JVM state'\<surd>"
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apply (clarsimp simp add: defs1 raise_xcpt_def map_eq_Cons
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                split: option.split)
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apply (frule conf_widen)
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apply assumption+
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apply (drule conf_RefTD)
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apply (clarsimp simp add: defs1)
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apply (rule conjI)
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 apply (drule widen_cfs_fields)
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 apply assumption+
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 apply (force intro: conf_widen simp add: hconf_def oconf_def lconf_def)
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apply blast
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done
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lemma Putfield_correct:
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"[| wf_prog wt G;
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  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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  ins!pc = Putfield F D; 
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  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
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  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
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  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
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==> G,phi \<turnstile>JVM state'\<surd>"
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apply (clarsimp simp add: defs1 raise_xcpt_def split: option.split List.split)
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apply (frule conf_widen)
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prefer 2
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  apply assumption
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 apply assumption
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apply (drule conf_RefTD)
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apply clarsimp
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apply (blast 
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       intro: 
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         hext_upd_obj approx_stk_sup_heap
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         approx_loc_sup_heap 
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         hconf_field_update
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         correct_frames_field_update conf_widen 
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       dest: 
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         widen_cfs_fields)
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done
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lemma New_correct:
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"[| wf_prog wt G;
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  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
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diff changeset
   147
  ins!pc = New X; 
10592
fc0b575a2cf7 BCV Integration
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diff changeset
   148
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
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diff changeset
   149
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
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diff changeset
   150
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
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diff changeset
   151
==> G,phi \<turnstile>JVM state'\<surd>"
10920
9b74eceea2d2 newref -> new_Addr
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diff changeset
   152
proof -
9b74eceea2d2 newref -> new_Addr
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diff changeset
   153
  assume wf:   "wf_prog wt G"
9b74eceea2d2 newref -> new_Addr
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diff changeset
   154
  assume meth: "method (G,C) sig = Some (C,rT,maxs,maxl,ins)"
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   155
  assume ins:  "ins!pc = New X"
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   156
  assume wt:   "wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc"
9b74eceea2d2 newref -> new_Addr
kleing
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diff changeset
   157
  assume exec: "Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs)"
9b74eceea2d2 newref -> new_Addr
kleing
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diff changeset
   158
  assume conf: "G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd>"
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   159
9b74eceea2d2 newref -> new_Addr
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diff changeset
   160
  from ins conf meth
9b74eceea2d2 newref -> new_Addr
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diff changeset
   161
  obtain ST LT where
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   162
    heap_ok:    "G\<turnstile>h hp\<surd>" and
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   163
    phi_pc:     "phi C sig!pc = Some (ST,LT)" and
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   164
    is_class_C: "is_class G C" and
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   165
    frame:      "correct_frame G hp (ST,LT) maxl ins (stk, loc, C, sig, pc)" and
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   166
    frames:     "correct_frames G hp phi rT sig frs"
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   167
    by (auto simp add: correct_state_def iff del: not_None_eq)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   168
10920
9b74eceea2d2 newref -> new_Addr
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diff changeset
   169
  from phi_pc ins wt
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   170
  obtain ST' LT' where
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   171
    is_class_X: "is_class G X" and
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   172
    maxs:       "maxs < length ST" and
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   173
    suc_pc:     "Suc pc < length ins" and
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   174
    phi_suc:    "phi C sig ! Suc pc = Some (ST', LT')" and
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   175
    less:       "G \<turnstile> (Class X # ST, LT) <=s (ST', LT')"
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   176
    by (unfold wt_instr_def step_def) auto
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   177
 
9b74eceea2d2 newref -> new_Addr
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diff changeset
   178
  obtain oref xp' where
9b74eceea2d2 newref -> new_Addr
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diff changeset
   179
    new_Addr: "(oref,xp') = new_Addr hp"
9b74eceea2d2 newref -> new_Addr
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diff changeset
   180
    by (cases "new_Addr hp") auto  
9b74eceea2d2 newref -> new_Addr
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diff changeset
   181
  hence cases: 
9b74eceea2d2 newref -> new_Addr
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diff changeset
   182
    "hp oref = None \<and> xp' = None \<or> xp' = Some OutOfMemory"
9b74eceea2d2 newref -> new_Addr
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diff changeset
   183
    by (blast dest: new_AddrD)
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   184
  moreover
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   185
  { assume "xp' = Some OutOfMemory"
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   186
    with exec ins meth new_Addr [symmetric]
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   187
    have "state' = (Some OutOfMemory, hp, (stk,loc,C,sig,Suc pc)#frs)" by simp
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   188
    hence ?thesis by (simp add: correct_state_def)
10920
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   189
  }
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   190
  moreover
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   191
  { assume hp: "hp oref = None" and "xp' = None"
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   192
    with exec ins meth new_Addr [symmetric]
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   193
    have state':
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   194
      "state' = Norm (hp(oref\<mapsto>(X, init_vars (fields (G, X)))), 
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   195
                      (Addr oref # stk, loc, C, sig, Suc pc) # frs)" 
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   196
      (is "state' = Norm (?hp', ?f # frs)")
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   197
      by simp    
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   198
    moreover
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   199
    from wf hp heap_ok is_class_X
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   200
    have hp': "G \<turnstile>h ?hp' \<surd>"
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   201
      by - (rule hconf_newref, 
10920
9b74eceea2d2 newref -> new_Addr
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parents: 10897
diff changeset
   202
            auto simp add: oconf_def dest: fields_is_type)
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   203
    moreover
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   204
    from hp
11085
b830bf10bf71 tuned for 99-2 release
kleing
parents: 10920
diff changeset
   205
    have sup: "hp \<le>| ?hp'" by (rule hext_new)
10920
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   206
    from hp frame less suc_pc wf
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   207
    have "correct_frame G ?hp' (ST', LT') maxl ins ?f"
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   208
      apply (unfold correct_frame_def sup_state_conv)
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   209
      apply (clarsimp simp add: map_eq_Cons conf_def fun_upd_apply approx_val_def)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   210
      apply (blast intro: approx_stk_sup_heap approx_loc_sup_heap sup)
10920
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   211
      done      
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   212
    moreover
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   213
    from hp frames wf heap_ok is_class_X
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   214
    have "correct_frames G ?hp' phi rT sig frs"
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   215
      by - (rule correct_frames_newref,
10920
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   216
            auto simp add: oconf_def dest: fields_is_type)
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   217
    ultimately
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   218
    have ?thesis
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   219
      by (simp add: is_class_C meth phi_suc correct_state_def del: not_None_eq)
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   220
  }
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   221
  ultimately
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   222
  show ?thesis by auto
9b74eceea2d2 newref -> new_Addr
kleing
parents: 10897
diff changeset
   223
qed
11085
b830bf10bf71 tuned for 99-2 release
kleing
parents: 10920
diff changeset
   224
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   225
lemmas [simp del] = split_paired_Ex
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   226
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   227
lemma Invoke_correct: 
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   228
"[| wt_jvm_prog G phi; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   229
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
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parents: 8011
diff changeset
   230
  ins ! pc = Invoke C' mn pTs; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   231
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   232
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   233
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   234
==> G,phi \<turnstile>JVM state'\<surd>" 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
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diff changeset
   235
proof -
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   236
  assume wtprog: "wt_jvm_prog G phi"
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   237
  assume method: "method (G,C) sig = Some (C,rT,maxs,maxl,ins)"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   238
  assume ins:    "ins ! pc = Invoke C' mn pTs"
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   239
  assume wti:    "wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   240
  assume state': "Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs)"
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   241
  assume approx: "G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   242
  
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   243
  from wtprog 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   244
  obtain wfmb where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   245
    wfprog: "wf_prog wfmb G" 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   246
    by (simp add: wt_jvm_prog_def)
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   247
      
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   248
  from ins method approx
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   249
  obtain s where
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   250
    heap_ok: "G\<turnstile>h hp\<surd>" and
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   251
    phi_pc:  "phi C sig!pc = Some s" and
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   252
    is_class_C: "is_class G C" and
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   253
    frame:   "correct_frame G hp s maxl ins (stk, loc, C, sig, pc)" and
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   254
    frames:  "correct_frames G hp phi rT sig frs"
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   255
    by (clarsimp simp add: correct_state_def iff del: not_None_eq)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   256
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   257
  from ins wti phi_pc
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   258
  obtain apTs X ST LT D' rT body where 
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   259
    is_class: "is_class G C'" and
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   260
    s:  "s = (rev apTs @ X # ST, LT)" and
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   261
    l:  "length apTs = length pTs" and
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   262
    X:  "G\<turnstile> X \<preceq> Class C'" and
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   263
    w:  "\<forall>x\<in>set (zip apTs pTs). x \<in> widen G" and
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   264
    mC':"method (G, C') (mn, pTs) = Some (D', rT, body)" and
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   265
    pc: "Suc pc < length ins" and
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   266
    step: "G \<turnstile> step (Invoke C' mn pTs) G (Some s) <=' phi C sig!Suc pc"
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   267
    by (simp add: wt_instr_def del: not_None_eq) (elim exE conjE, rule that)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   268
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   269
  from step
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   270
  obtain ST' LT' where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   271
    s': "phi C sig ! Suc pc = Some (ST', LT')"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   272
    by (simp add: step_def split_paired_Ex) (elim, rule that)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   273
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   274
  from X 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   275
  obtain T where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   276
    X_Ref: "X = RefT T"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   277
    by - (drule widen_RefT2, erule exE, rule that)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   278
  
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   279
  from s ins frame 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   280
  obtain 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   281
    a_stk: "approx_stk G hp stk (rev apTs @ X # ST)" and
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   282
    a_loc: "approx_loc G hp loc LT" and
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   283
    suc_l: "length loc = Suc (length (snd sig) + maxl)"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   284
    by (simp add: correct_frame_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   285
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   286
  from a_stk
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   287
  obtain opTs stk' oX where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   288
    opTs:   "approx_stk G hp opTs (rev apTs)" and
10496
f2d304bdf3cc BCV integration (first step)
kleing
parents: 10387
diff changeset
   289
    oX:     "approx_val G hp oX (OK X)" and
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   290
    a_stk': "approx_stk G hp stk' ST" and
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   291
    stk':   "stk = opTs @ oX # stk'" and
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   292
    l_o:    "length opTs = length apTs" 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   293
            "length stk' = length ST"  
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   294
    by - (drule approx_stk_append, simp, elim, simp)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   295
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   296
  from oX 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   297
  have "\<exists>T'. typeof (option_map obj_ty \<circ> hp) oX = Some T' \<and> G \<turnstile> T' \<preceq> X"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   298
    by (clarsimp simp add: approx_val_def conf_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   299
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   300
  with X_Ref
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   301
  obtain T' where
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   302
    oX_Ref: "typeof (option_map obj_ty \<circ> hp) oX = Some (RefT T')"
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   303
            "G \<turnstile> RefT T' \<preceq> X" 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   304
    apply (elim, simp)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   305
    apply (frule widen_RefT2)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   306
    by (elim, simp)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   307
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   308
  from stk' l_o l
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   309
  have oX_pos: "last (take (Suc (length pTs)) stk) = oX" by simp
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   310
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   311
  with state' method ins 
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   312
  have Null_ok: "oX = Null ==> ?thesis"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   313
    by (simp add: correct_state_def raise_xcpt_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   314
  
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   315
  { fix ref assume oX_Addr: "oX = Addr ref"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   316
    
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   317
    with oX_Ref
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   318
    obtain obj where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   319
      loc: "hp ref = Some obj" "obj_ty obj = RefT T'"
10387
9dac2cad5500 adapted "obtain" proofs;
wenzelm
parents: 10056
diff changeset
   320
      by auto
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   321
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   322
    then 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   323
    obtain D where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   324
      obj_ty: "obj_ty obj = Class D"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   325
      by (auto simp add: obj_ty_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   326
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   327
    with X_Ref oX_Ref loc
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   328
    obtain D: "G \<turnstile> Class D \<preceq> X"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   329
      by simp
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   330
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   331
    with X_Ref
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   332
    obtain X' where 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   333
      X': "X = Class X'"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   334
      by - (drule widen_Class, elim, rule that)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   335
      
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   336
    with X
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   337
    have X'_subcls: "G \<turnstile> X' \<preceq>C C'" 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   338
      by simp
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   339
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   340
    with mC' wfprog
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   341
    obtain D0 rT0 maxs0 maxl0 ins0 where
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   342
      mX: "method (G, X') (mn, pTs) = Some (D0, rT0, maxs0, maxl0, ins0)" "G\<turnstile>rT0\<preceq>rT"
10387
9dac2cad5500 adapted "obtain" proofs;
wenzelm
parents: 10056
diff changeset
   343
      by (auto dest: subtype_widen_methd intro: that)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   344
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   345
    from X' D
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   346
    have D_subcls: "G \<turnstile> D \<preceq>C X'" 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   347
      by simp
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   348
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   349
    with wfprog mX
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   350
    obtain D'' rT' mxs' mxl' ins' where
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   351
      mD: "method (G, D) (mn, pTs) = Some (D'', rT', mxs', mxl', ins')" 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   352
          "G \<turnstile> rT' \<preceq> rT0"
10387
9dac2cad5500 adapted "obtain" proofs;
wenzelm
parents: 10056
diff changeset
   353
      by (auto dest: subtype_widen_methd intro: that)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   354
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   355
    from mX mD
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   356
    have rT': "G \<turnstile> rT' \<preceq> rT"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   357
      by - (rule widen_trans)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   358
    
10612
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   359
    from is_class X'_subcls D_subcls
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   360
    have is_class_D: "is_class G D"
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   361
    by (auto dest: subcls_is_class2)
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   362
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   363
    with mD wfprog
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   364
    obtain mD'': 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   365
      "method (G, D'') (mn, pTs) = Some (D'', rT', mxs', mxl', ins')"
10612
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   366
      "is_class G D''"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   367
      by (auto dest: method_in_md)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   368
      
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   369
    from loc obj_ty
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   370
    have "fst (the (hp ref)) = D"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   371
      by (simp add: obj_ty_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   372
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   373
    with oX_Addr oX_pos state' method ins stk' l_o l loc obj_ty mD 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   374
    have state'_val:
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   375
      "state' =
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   376
       Norm (hp, ([], Addr ref # rev opTs @ replicate mxl' arbitrary, 
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   377
                  D'', (mn, pTs), 0) # (stk', loc, C, sig, Suc pc) # frs)"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   378
      (is "state' = Norm (hp, ?f # ?f' # frs)")
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   379
      by (simp add: raise_xcpt_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   380
    
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   381
    from wtprog mD''
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   382
    have start: "wt_start G D'' pTs mxl' (phi D'' (mn, pTs)) \<and> ins' \<noteq> []"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   383
      by (auto dest: wt_jvm_prog_impl_wt_start)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   384
    
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   385
    then
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   386
    obtain LT0 where
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   387
      LT0: "phi D'' (mn, pTs) ! 0 = Some ([], LT0)"
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   388
      by (clarsimp simp add: wt_start_def sup_state_conv)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   389
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   390
    have c_f: "correct_frame G hp ([], LT0) mxl' ins' ?f"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   391
    proof -
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   392
      from start LT0
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   393
      have sup_loc: 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   394
        "G \<turnstile> (OK (Class D'') # map OK pTs @ replicate mxl' Err) <=l LT0"
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   395
        (is "G \<turnstile> ?LT <=l LT0")
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   396
        by (simp add: wt_start_def sup_state_conv)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   397
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   398
      have r: "approx_loc G hp (replicate mxl' arbitrary) (replicate mxl' Err)"
10056
9f84ffa4a8d0 tuned spacing for document generation
kleing
parents: 10042
diff changeset
   399
        by (simp add: approx_loc_def approx_val_Err 
9f84ffa4a8d0 tuned spacing for document generation
kleing
parents: 10042
diff changeset
   400
                      list_all2_def set_replicate_conv_if)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   401
10612
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   402
      from wfprog mD is_class_D
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   403
      have "G \<turnstile> Class D \<preceq> Class D''"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   404
        by (auto dest: method_wf_mdecl)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   405
      with obj_ty loc
10496
f2d304bdf3cc BCV integration (first step)
kleing
parents: 10387
diff changeset
   406
      have a: "approx_val G hp (Addr ref) (OK (Class D''))"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   407
        by (simp add: approx_val_def conf_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   408
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   409
      from opTs w l l_o wfprog 
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   410
      have "approx_stk G hp opTs (rev pTs)" 
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   411
	by (auto elim!: approx_stk_all_widen simp add: zip_rev)
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   412
      hence "approx_stk G hp (rev opTs) pTs" by (subst approx_stk_rev)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   413
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   414
      with r a l_o l
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   415
      have "approx_loc G hp (Addr ref # rev opTs @ replicate mxl' arbitrary) ?LT"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   416
        (is "approx_loc G hp ?lt ?LT")
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   417
        by (auto simp add: approx_loc_append approx_stk_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   418
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   419
      from this sup_loc wfprog
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   420
      have "approx_loc G hp ?lt LT0" by (rule approx_loc_widen)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   421
      with start l_o l
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   422
      show ?thesis by (simp add: correct_frame_def)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   423
    qed
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   424
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   425
    have c_f': "correct_frame G hp (tl ST', LT') maxl ins ?f'"
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   426
    proof -    
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   427
      from s s' mC' step l
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   428
      have "G \<turnstile> LT <=l LT'"
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   429
        by (simp add: step_def sup_state_conv)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   430
      with wfprog a_loc
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   431
      have a: "approx_loc G hp loc LT'"
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   432
        by - (rule approx_loc_widen)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   433
      moreover
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   434
      from s s' mC' step l
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   435
      have  "G \<turnstile> map OK ST <=l map OK (tl ST')"
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   436
        by (auto simp add: step_def sup_state_conv map_eq_Cons)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   437
      with wfprog a_stk'
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   438
      have "approx_stk G hp stk' (tl ST')"
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   439
        by - (rule approx_stk_widen)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   440
      ultimately
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   441
      show ?thesis by (simp add: correct_frame_def suc_l pc)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   442
    qed
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   443
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   444
    with state'_val heap_ok mD'' ins method phi_pc s X' l 
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   445
         frames s' LT0 c_f c_f' is_class_C
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   446
    have ?thesis 
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   447
      by (simp add: correct_state_def) (intro exI conjI, blast, assumption+)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   448
  }
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   449
  
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   450
  with Null_ok oX_Ref
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   451
  show "G,phi \<turnstile>JVM state'\<surd>" by - (cases oX, auto)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   452
qed
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   453
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   454
lemmas [simp del] = map_append
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   455
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   456
lemma Return_correct:
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   457
"[| wt_jvm_prog G phi; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   458
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   459
  ins ! pc = Return; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   460
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   461
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   462
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   463
==> G,phi \<turnstile>JVM state'\<surd>"
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   464
apply (clarsimp simp add: neq_Nil_conv defs1 split: split_if_asm iff del: not_None_eq)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   465
apply (frule wt_jvm_prog_impl_wt_instr)
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   466
apply (assumption, assumption, erule Suc_lessD)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   467
apply (clarsimp simp add: map_eq_Cons append_eq_conv_conj defs1)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   468
apply (unfold wt_jvm_prog_def)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   469
apply (frule subcls_widen_methd, assumption+)
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   470
apply clarify
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   471
apply simp
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   472
apply (erule conf_widen, assumption)
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   473
apply (erule widen_trans)+
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   474
apply blast
9819
wenzelm
parents: 9757
diff changeset
   475
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   476
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   477
lemmas [simp] = map_append
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   478
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   479
lemma Goto_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   480
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   481
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   482
  ins ! pc = Goto branch; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   483
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   484
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   485
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   486
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   487
apply (clarsimp simp add: defs1)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   488
apply fast
9819
wenzelm
parents: 9757
diff changeset
   489
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   490
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   491
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   492
lemma Ifcmpeq_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   493
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   494
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   495
  ins ! pc = Ifcmpeq branch; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   496
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   497
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   498
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   499
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   500
apply (clarsimp simp add: defs1)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   501
apply fast
9819
wenzelm
parents: 9757
diff changeset
   502
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   503
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   504
lemma Pop_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   505
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   506
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   507
  ins ! pc = Pop;
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   508
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   509
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   510
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   511
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   512
apply (clarsimp simp add: defs1)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   513
apply fast
9819
wenzelm
parents: 9757
diff changeset
   514
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   515
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   516
lemma Dup_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   517
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   518
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   519
  ins ! pc = Dup;
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   520
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   521
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   522
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   523
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   524
apply (clarsimp simp add: defs1 map_eq_Cons)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   525
apply (blast intro: conf_widen)
9819
wenzelm
parents: 9757
diff changeset
   526
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   527
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   528
lemma Dup_x1_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   529
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   530
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   531
  ins ! pc = Dup_x1;
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   532
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   533
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   534
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   535
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   536
apply (clarsimp simp add: defs1 map_eq_Cons)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   537
apply (blast intro: conf_widen)
9819
wenzelm
parents: 9757
diff changeset
   538
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   539
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   540
lemma Dup_x2_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   541
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   542
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   543
  ins ! pc = Dup_x2;
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   544
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   545
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   546
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   547
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   548
apply (clarsimp simp add: defs1 map_eq_Cons)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   549
apply (blast intro: conf_widen)
9819
wenzelm
parents: 9757
diff changeset
   550
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   551
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   552
lemma Swap_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   553
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   554
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   555
  ins ! pc = Swap;
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   556
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   557
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   558
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   559
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   560
apply (clarsimp simp add: defs1 map_eq_Cons)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   561
apply (blast intro: conf_widen)
9819
wenzelm
parents: 9757
diff changeset
   562
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   563
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   564
lemma IAdd_correct:
10042
7164dc0d24d8 unsymbolized
kleing
parents: 9941
diff changeset
   565
"[| wf_prog wt G; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   566
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   567
  ins ! pc = IAdd; 
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   568
  wt_instr (ins!pc) G rT (phi C sig) maxs (length ins) pc; 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   569
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs) ; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   570
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   571
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   572
apply (clarsimp simp add: defs1 map_eq_Cons approx_val_def conf_def)
11252
71c00cb091d2 cleanup, tuned
kleing
parents: 11085
diff changeset
   573
apply blast
9819
wenzelm
parents: 9757
diff changeset
   574
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   575
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   576
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   577
lemma instr_correct:
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   578
"[| wt_jvm_prog G phi;
10592
fc0b575a2cf7 BCV Integration
kleing
parents: 10496
diff changeset
   579
  method (G,C) sig = Some (C,rT,maxs,maxl,ins); 
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   580
  Some state' = exec (G, None, hp, (stk,loc,C,sig,pc)#frs); 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   581
  G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> |] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   582
==> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   583
apply (frule wt_jvm_prog_impl_wt_instr_cor)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   584
apply assumption+
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   585
apply (cases "ins!pc")
10897
697fab84709e removed instructions Aconst_null+Bipush, introduced LitPush
kleing
parents: 10812
diff changeset
   586
prefer 8
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   587
apply (rule Invoke_correct, assumption+)
10897
697fab84709e removed instructions Aconst_null+Bipush, introduced LitPush
kleing
parents: 10812
diff changeset
   588
prefer 8
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   589
apply (rule Return_correct, assumption+)
10612
779af7c58743 improved superclass entry for classes and definition status of is_class, class
oheimb
parents: 10592
diff changeset
   590
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   591
apply (unfold wt_jvm_prog_def)
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   592
apply (rule Load_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   593
apply (rule Store_correct, assumption+)
10897
697fab84709e removed instructions Aconst_null+Bipush, introduced LitPush
kleing
parents: 10812
diff changeset
   594
apply (rule LitPush_correct, assumption+)
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   595
apply (rule New_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   596
apply (rule Getfield_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   597
apply (rule Putfield_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   598
apply (rule Checkcast_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   599
apply (rule Pop_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   600
apply (rule Dup_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   601
apply (rule Dup_x1_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   602
apply (rule Dup_x2_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   603
apply (rule Swap_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   604
apply (rule IAdd_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   605
apply (rule Goto_correct, assumption+)
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   606
apply (rule Ifcmpeq_correct, assumption+)
9819
wenzelm
parents: 9757
diff changeset
   607
done
10626
46bcddfe9e7b update for changes in Correct.thy and class/is_class defs
kleing
parents: 10612
diff changeset
   608
11085
b830bf10bf71 tuned for 99-2 release
kleing
parents: 10920
diff changeset
   609
section {* Main *}
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   610
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   611
lemma correct_state_impl_Some_method:
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   612
  "G,phi \<turnstile>JVM (None, hp, (stk,loc,C,sig,pc)#frs)\<surd> 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   613
  ==> \<exists>meth. method (G,C) sig = Some(C,meth)"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   614
by (auto simp add: correct_state_def Let_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   615
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   616
9941
fe05af7ec816 renamed atts: rulify to rule_format, elimify to elim_format;
wenzelm
parents: 9906
diff changeset
   617
lemma BV_correct_1 [rule_format]:
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   618
"!!state. [| wt_jvm_prog G phi; G,phi \<turnstile>JVM state\<surd>|] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   619
 ==> exec (G,state) = Some state' --> G,phi \<turnstile>JVM state'\<surd>"
9819
wenzelm
parents: 9757
diff changeset
   620
apply (simp only: split_tupled_all)
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   621
apply (rename_tac xp hp frs)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   622
apply (case_tac xp)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   623
 apply (case_tac frs)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   624
  apply simp
9819
wenzelm
parents: 9757
diff changeset
   625
 apply (simp only: split_tupled_all)
wenzelm
parents: 9757
diff changeset
   626
 apply hypsubst
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   627
 apply (frule correct_state_impl_Some_method)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   628
 apply (force intro: instr_correct)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   629
apply (case_tac frs)
9819
wenzelm
parents: 9757
diff changeset
   630
apply simp_all
wenzelm
parents: 9757
diff changeset
   631
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   632
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   633
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   634
lemma L0:
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   635
  "[| xp=None; frs\<noteq>[] |] ==> (\<exists>state'. exec (G,xp,hp,frs) = Some state')"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   636
by (clarsimp simp add: neq_Nil_conv simp del: split_paired_Ex)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   637
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   638
lemma L1:
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   639
  "[|wt_jvm_prog G phi; G,phi \<turnstile>JVM (xp,hp,frs)\<surd>; xp=None; frs\<noteq>[]|] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   640
  ==> \<exists>state'. exec(G,xp,hp,frs) = Some state' \<and> G,phi \<turnstile>JVM state'\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   641
apply (drule L0)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   642
apply assumption
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   643
apply (fast intro: BV_correct_1)
9819
wenzelm
parents: 9757
diff changeset
   644
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   645
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   646
9941
fe05af7ec816 renamed atts: rulify to rule_format, elimify to elim_format;
wenzelm
parents: 9906
diff changeset
   647
theorem BV_correct [rule_format]:
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   648
"[| wt_jvm_prog G phi; G \<turnstile> s -jvm-> t |] ==> G,phi \<turnstile>JVM s\<surd> --> G,phi \<turnstile>JVM t\<surd>"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   649
apply (unfold exec_all_def)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   650
apply (erule rtrancl_induct)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   651
 apply simp
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   652
apply (auto intro: BV_correct_1)
9819
wenzelm
parents: 9757
diff changeset
   653
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   654
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   655
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   656
theorem BV_correct_initial:
10056
9f84ffa4a8d0 tuned spacing for document generation
kleing
parents: 10042
diff changeset
   657
"[| wt_jvm_prog G phi; 
10812
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   658
    G \<turnstile> s0 -jvm-> (None,hp,(stk,loc,C,sig,pc)#frs); G,phi \<turnstile>JVM s0 \<surd>|] 
ead84e90bfeb merged semilattice orders with <=' from Convert.thy (now defined in JVMType.thy)
kleing
parents: 10763
diff changeset
   659
==> approx_stk G hp stk (fst (the (((phi  C)  sig) ! pc))) \<and> 
10056
9f84ffa4a8d0 tuned spacing for document generation
kleing
parents: 10042
diff changeset
   660
    approx_loc G hp loc (snd (the (((phi  C)  sig) ! pc)))"
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   661
apply (drule BV_correct)
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   662
apply assumption+
10056
9f84ffa4a8d0 tuned spacing for document generation
kleing
parents: 10042
diff changeset
   663
apply (simp add: correct_state_def correct_frame_def split_def 
9f84ffa4a8d0 tuned spacing for document generation
kleing
parents: 10042
diff changeset
   664
            split: option.splits)
9819
wenzelm
parents: 9757
diff changeset
   665
done
9757
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   666
1024a2d80ac0 functional LBV style, dead code, type safety -> Isar
kleing
parents: 8011
diff changeset
   667
end