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(*
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File: MIlive.ML
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Author: Stephan Merz
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Copyright: 1997 University of Munich
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RPC-Memory example: Lower-level lemmas for the liveness proof
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*)
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(* Liveness assertions for the different implementation states, based on the
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fairness conditions. Prove subgoals of WF1 / SF1 rules as separate lemmas
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for readability. Reuse action proofs from safety part.
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*)
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(* ------------------------------ State S1 ------------------------------ *)
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qed_goal "S1_successors" MemoryImplementation.thy
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"|- $S1 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> (S1 rmhist p)` | (S2 rmhist p)`"
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(fn _ => [split_idle_tac [] 1,
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auto_tac (MI_css addSDs2 [Step1_2_1])
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]);
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(* Show that the implementation can satisfy the high-level fairness requirements
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by entering the state S1 infinitely often.
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*)
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qed_goal "S1_RNextdisabled" MemoryImplementation.thy
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"|- S1 rmhist p --> \
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\ ~Enabled (<RNext memCh mm (resbar rmhist) p>_(rtrner memCh!p, resbar rmhist!p))"
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(fn _ => [action_simp_tac (simpset() addsimps [angle_def,S_def,S1_def])
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[notI] [enabledE,temp_elim Memoryidle] 1,
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Force_tac 1
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]);
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qed_goal "S1_Returndisabled" MemoryImplementation.thy
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"|- S1 rmhist p --> \
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\ ~Enabled (<MemReturn memCh (resbar rmhist) p>_(rtrner memCh!p, resbar rmhist!p))"
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4089
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(fn _ => [action_simp_tac (simpset() addsimps [angle_def,MemReturn_def,Return_def,S_def,S1_def])
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[notI] [enabledE] 1
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]);
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qed_goal "RNext_fair" MemoryImplementation.thy
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"|- []<>S1 rmhist p \
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\ --> WF(RNext memCh mm (resbar rmhist) p)_(rtrner memCh!p, resbar rmhist!p)"
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(fn _ => [auto_tac (MI_css addsimps2 [WF_alt]
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addSIs2 [S1_RNextdisabled] addSEs2 [STL4E,DmdImplE])
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]);
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qed_goal "Return_fair" MemoryImplementation.thy
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"|- []<>S1 rmhist p \
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\ --> WF(MemReturn memCh (resbar rmhist) p)_(rtrner memCh!p, resbar rmhist!p)"
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(fn _ => [auto_tac (MI_css addsimps2 [WF_alt]
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addSIs2 [S1_Returndisabled] addSEs2 [STL4E,DmdImplE])
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]);
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(* ------------------------------ State S2 ------------------------------ *)
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qed_goal "S2_successors" MemoryImplementation.thy
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"|- $S2 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> (S2 rmhist p)` | (S3 rmhist p)`"
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(fn _ => [split_idle_tac [] 1,
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auto_tac (MI_css addSDs2 [Step1_2_2])
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]);
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qed_goal "S2MClkFwd_successors" MemoryImplementation.thy
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"|- ($S2 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) \
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\ & <MClkFwd memCh crCh cst p>_(c p) \
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\ --> (S3 rmhist p)`"
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(fn _ => [ auto_tac (MI_css addsimps2 [angle_def] addSDs2 [Step1_2_2]) ]);
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qed_goal "S2MClkFwd_enabled" MemoryImplementation.thy
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"|- $S2 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> $Enabled (<MClkFwd memCh crCh cst p>_(c p))"
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(fn _ => [auto_tac (MI_css addsimps2 [c_def] addSIs2 [MClkFwd_ch_enabled,MClkFwd_enabled]),
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cut_facts_tac [MI_base] 1,
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blast_tac (claset() addDs [base_pair]) 1,
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ALLGOALS (asm_full_simp_tac (simpset() addsimps [S_def,S2_def]))
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]);
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qed_goal "S2_live" MemoryImplementation.thy
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"|- [](ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) & WF(MClkFwd memCh crCh cst p)_(c p) \
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\ --> (S2 rmhist p ~> S3 rmhist p)"
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(fn _ => [REPEAT (resolve_tac [WF1,S2_successors,
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S2MClkFwd_successors,S2MClkFwd_enabled] 1)
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]);
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(* ------------------------------ State S3 ------------------------------ *)
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qed_goal "S3_successors" MemoryImplementation.thy
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"|- $S3 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> (S3 rmhist p)` | (S4 rmhist p | S6 rmhist p)`"
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(fn _ => [split_idle_tac [] 1,
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auto_tac (MI_css addSDs2 [Step1_2_3])
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]);
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qed_goal "S3RPC_successors" MemoryImplementation.thy
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"|- ($S3 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) \
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\ & <RPCNext crCh rmCh rst p>_(r p) \
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\ --> (S4 rmhist p | S6 rmhist p)`"
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(fn _ => [ auto_tac (MI_css addsimps2 [angle_def] addSDs2 [Step1_2_3]) ]);
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qed_goal "S3RPC_enabled" MemoryImplementation.thy
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"|- $S3 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> $Enabled (<RPCNext crCh rmCh rst p>_(r p))"
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(fn _ => [auto_tac (MI_css addsimps2 [r_def]
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addSIs2 [RPCFail_Next_enabled,RPCFail_enabled]),
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cut_facts_tac [MI_base] 1,
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blast_tac (claset() addDs [base_pair]) 1,
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ALLGOALS (asm_full_simp_tac (simpset() addsimps [S_def,S3_def]))
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]);
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qed_goal "S3_live" MemoryImplementation.thy
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"|- [](ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) & WF(RPCNext crCh rmCh rst p)_(r p) \
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\ --> (S3 rmhist p ~> S4 rmhist p | S6 rmhist p)"
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(fn _ => [REPEAT (resolve_tac [WF1,S3_successors,S3RPC_successors,S3RPC_enabled] 1)]);
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(* ------------- State S4 -------------------------------------------------- *)
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qed_goal "S4_successors" MemoryImplementation.thy
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"|- $S4 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ & (!l. $MemInv mm l) \
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\ --> (S4 rmhist p)` | (S5 rmhist p)`"
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(fn _ => [split_idle_tac [] 1,
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auto_tac (MI_css addSDs2 [Step1_2_4])
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]);
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(* ------------- State S4a: S4 /\ (ires p = NotAResult) ------------------------------ *)
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qed_goal "S4a_successors" MemoryImplementation.thy
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"|- $(S4 rmhist p & ires!p = #NotAResult) \
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\ & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l) \
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\ --> (S4 rmhist p & ires!p = #NotAResult)` \
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\ | ((S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p)`"
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(fn _ => [split_idle_tac [m_def] 1,
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auto_tac (MI_css addSDs2 [Step1_2_4])
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]);
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qed_goal "S4aRNext_successors" MemoryImplementation.thy
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"|- ($(S4 rmhist p & ires!p = #NotAResult) \
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\ & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l)) \
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\ & <RNext rmCh mm ires p>_(m p) \
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\ --> ((S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p)`"
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(fn _ => [auto_tac (MI_css addsimps2 [angle_def]
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addSDs2 [Step1_2_4, ReadResult, WriteResult])
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]);
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qed_goal "S4aRNext_enabled" MemoryImplementation.thy
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"|- $(S4 rmhist p & ires!p = #NotAResult) \
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\ & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l) \
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\ --> $Enabled (<RNext rmCh mm ires p>_(m p))"
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(fn _ => [auto_tac (MI_css addsimps2 [m_def] addSIs2 [RNext_enabled]),
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cut_facts_tac [MI_base] 1,
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blast_tac (claset() addDs [base_pair]) 1,
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asm_full_simp_tac (simpset() addsimps [S_def,S4_def]) 1
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]);
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qed_goal "S4a_live" MemoryImplementation.thy
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"|- [](ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l)) \
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\ & WF(RNext rmCh mm ires p)_(m p) \
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\ --> (S4 rmhist p & ires!p = #NotAResult \
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\ ~> (S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p)"
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(K [REPEAT (resolve_tac [WF1, S4a_successors, S4aRNext_successors, S4aRNext_enabled] 1)]);
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(* ------------- State S4b: S4 /\ (ires p # NotAResult) ------------------------------ *)
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qed_goal "S4b_successors" MemoryImplementation.thy
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"|- $(S4 rmhist p & ires!p ~= #NotAResult) \
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\ & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l) \
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\ --> (S4 rmhist p & ires!p ~= #NotAResult)` | (S5 rmhist p)`"
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(fn _ => [split_idle_tac [m_def] 1,
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auto_tac (MI_css addSDs2 [WriteResult,Step1_2_4,ReadResult])
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]);
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qed_goal "S4bReturn_successors" MemoryImplementation.thy
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"|- ($(S4 rmhist p & ires!p ~= #NotAResult) \
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\ & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l)) \
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\ & <MemReturn rmCh ires p>_(m p) \
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\ --> (S5 rmhist p)`"
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(fn _ => [force_tac (MI_css addsimps2 [angle_def] addSDs2 [Step1_2_4]
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addDs2 [ReturnNotReadWrite]) 1
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]);
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qed_goal "S4bReturn_enabled" MemoryImplementation.thy
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"|- $(S4 rmhist p & ires!p ~= #NotAResult) \
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\ & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l) \
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\ --> $Enabled (<MemReturn rmCh ires p>_(m p))"
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(fn _ => [auto_tac (MI_css addsimps2 [m_def] addSIs2 [MemReturn_enabled]),
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cut_facts_tac [MI_base] 1,
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blast_tac (claset() addDs [base_pair]) 1,
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asm_full_simp_tac (simpset() addsimps [S_def,S4_def]) 1
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]);
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qed_goal "S4b_live" MemoryImplementation.thy
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"|- [](ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & (!l. $MemInv mm l)) \
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\ & WF(MemReturn rmCh ires p)_(m p) \
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\ --> (S4 rmhist p & ires!p ~= #NotAResult ~> S5 rmhist p)"
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(K [REPEAT (resolve_tac [WF1, S4b_successors,S4bReturn_successors, S4bReturn_enabled] 1)]);
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(* ------------------------------ State S5 ------------------------------ *)
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qed_goal "S5_successors" MemoryImplementation.thy
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"|- $S5 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> (S5 rmhist p)` | (S6 rmhist p)`"
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(fn _ => [split_idle_tac [] 1,
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auto_tac (MI_css addSDs2 [Step1_2_5])
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]);
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qed_goal "S5RPC_successors" MemoryImplementation.thy
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"|- ($S5 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) \
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\ & <RPCNext crCh rmCh rst p>_(r p) \
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\ --> (S6 rmhist p)`"
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(fn _ => [ auto_tac (MI_css addsimps2 [angle_def] addSDs2 [Step1_2_5]) ]);
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qed_goal "S5RPC_enabled" MemoryImplementation.thy
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"|- $S5 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> $Enabled (<RPCNext crCh rmCh rst p>_(r p))"
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(fn _ => [auto_tac (MI_css addsimps2 [r_def]
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addSIs2 [RPCFail_Next_enabled, RPCFail_enabled]),
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cut_facts_tac [MI_base] 1,
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blast_tac (claset() addDs [base_pair]) 1,
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ALLGOALS (asm_full_simp_tac (simpset() addsimps [S_def,S5_def]))
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]);
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qed_goal "S5_live" MemoryImplementation.thy
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"|- [](ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) \
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\ & WF(RPCNext crCh rmCh rst p)_(r p) \
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\ --> (S5 rmhist p ~> S6 rmhist p)"
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(fn _ => [REPEAT (resolve_tac [WF1,S5_successors,S5RPC_successors,S5RPC_enabled] 1)]);
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(* ------------------------------ State S6 ------------------------------ *)
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qed_goal "S6_successors" MemoryImplementation.thy
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6255
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"|- $S6 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) \
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\ --> (S1 rmhist p)` | (S3 rmhist p)` | (S6 rmhist p)`"
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(fn _ => [split_idle_tac [] 1,
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auto_tac (MI_css addSDs2 [Step1_2_6])
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]);
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qed_goal "S6MClkReply_successors" MemoryImplementation.thy
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"|- ($S6 rmhist p & ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p)) \
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\ & <MClkReply memCh crCh cst p>_(c p) \
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\ --> (S1 rmhist p)`"
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(fn _ => [auto_tac (MI_css addsimps2 [angle_def] addSDs2 [Step1_2_6, MClkReplyNotRetry])
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]);
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qed_goal "MClkReplyS6" MemoryImplementation.thy
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"|- $ImpInv rmhist p & <MClkReply memCh crCh cst p>_(c p) --> $S6 rmhist p"
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(fn _ => [action_simp_tac
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(simpset() addsimps
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[angle_def,MClkReply_def,Return_def,
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ImpInv_def,S_def,S1_def,S2_def,S3_def,S4_def,S5_def])
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[] [] 1
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]);
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qed_goal "S6MClkReply_enabled" MemoryImplementation.thy
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"|- S6 rmhist p --> Enabled (<MClkReply memCh crCh cst p>_(c p))"
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(fn _ => [auto_tac (MI_css addsimps2 [c_def] addSIs2 [MClkReply_enabled]),
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cut_facts_tac [MI_base] 1,
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blast_tac (claset() addDs [base_pair]) 1,
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ALLGOALS (action_simp_tac (simpset() addsimps [S_def,S6_def]) [] [])
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]);
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qed_goal "S6_live" MemoryImplementation.thy
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"|- [](ImpNext p & [HNext rmhist p]_(c p,r p,m p, rmhist!p) & $(ImpInv rmhist p)) \
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\ & SF(MClkReply memCh crCh cst p)_(c p) & []<>(S6 rmhist p) \
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\ --> []<>(S1 rmhist p)"
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(fn _ => [Clarsimp_tac 1,
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subgoal_tac "sigma |= []<>(<MClkReply memCh crCh cst p>_(c p))" 1,
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etac InfiniteEnsures 1, atac 1,
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action_simp_tac (simpset()) []
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(map temp_elim [MClkReplyS6,S6MClkReply_successors]) 1,
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auto_tac (MI_css addsimps2 [SF_def]),
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etac swap 1,
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auto_tac (MI_css addSIs2 [S6MClkReply_enabled] addSEs2 [STL4E, DmdImplE])
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]);
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(* ------------------------------ complex leadsto properties ------------------------------ *)
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qed_goal "S5S6LeadstoS6" MemoryImplementation.thy
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6255
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"!!sigma. sigma |= S5 rmhist p ~> S6 rmhist p \
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\ ==> sigma |= (S5 rmhist p | S6 rmhist p) ~> S6 rmhist p"
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(fn _ => [auto_tac (MI_css addSIs2 [LatticeDisjunctionIntro, LatticeReflexivity])
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3807
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]);
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qed_goal "S4bS5S6LeadstoS6" MemoryImplementation.thy
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6255
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"!!sigma. [| sigma |= S4 rmhist p & ires!p ~= #NotAResult ~> S5 rmhist p; \
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\ sigma |= S5 rmhist p ~> S6 rmhist p |] \
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\ ==> sigma |= (S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p | S6 rmhist p \
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\ ~> S6 rmhist p"
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3807
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(fn _ => [auto_tac (MI_css addSIs2 [LatticeDisjunctionIntro,S5S6LeadstoS6]
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addIs2 [LatticeTransitivity])
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]);
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qed_goal "S4S5S6LeadstoS6" MemoryImplementation.thy
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6255
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"!!sigma. [| sigma |= S4 rmhist p & ires!p = #NotAResult \
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\ ~> (S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p; \
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\ sigma |= S4 rmhist p & ires!p ~= #NotAResult ~> S5 rmhist p; \
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\ sigma |= S5 rmhist p ~> S6 rmhist p |] \
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\ ==> sigma |= S4 rmhist p | S5 rmhist p | S6 rmhist p ~> S6 rmhist p"
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(fn _ => [subgoal_tac "sigma |= (S4 rmhist p & ires!p = #NotAResult) | (S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p | S6 rmhist p ~> S6 rmhist p" 1,
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eres_inst_tac [("G", "PRED ((S4 rmhist p & ires!p = #NotAResult) | (S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p | S6 rmhist p)")] (temp_use LatticeTransitivity) 1,
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force_tac (MI_css addsimps2 Init_defs addSIs2 [ImplLeadsto_gen, necT]) 1,
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rtac (temp_use LatticeDisjunctionIntro) 1,
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etac (temp_use LatticeTransitivity) 1,
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etac (temp_use LatticeTriangle2) 1, atac 1,
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3807
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auto_tac (MI_css addSIs2 [S4bS5S6LeadstoS6])
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]);
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qed_goal "S3S4S5S6LeadstoS6" MemoryImplementation.thy
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6255
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"!!sigma. [| sigma |= S3 rmhist p ~> S4 rmhist p | S6 rmhist p; \
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\ sigma |= S4 rmhist p & ires!p = #NotAResult \
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\ ~> (S4 rmhist p & ires!p ~= #NotAResult) | S5 rmhist p; \
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\ sigma |= S4 rmhist p & ires!p ~= #NotAResult ~> S5 rmhist p; \
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\ sigma |= S5 rmhist p ~> S6 rmhist p |] \
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\ ==> sigma |= S3 rmhist p | S4 rmhist p | S5 rmhist p | S6 rmhist p ~> S6 rmhist p"
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(fn _ => [rtac (temp_use LatticeDisjunctionIntro) 1,
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etac (temp_use LatticeTriangle2) 1,
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rtac (S4S5S6LeadstoS6 RS (temp_use LatticeTransitivity)) 1,
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auto_tac (MI_css addSIs2 [S4S5S6LeadstoS6,necT]
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addIs2 [ImplLeadsto_gen] addsimps2 Init_defs)
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3807
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]);
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qed_goal "S2S3S4S5S6LeadstoS6" MemoryImplementation.thy
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6255
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"!!sigma. [| sigma |= S2 rmhist p ~> S3 rmhist p; \
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\ sigma |= S3 rmhist p ~> S4 rmhist p | S6 rmhist p; \
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\ sigma |= S4 rmhist p & ires!p = #NotAResult \
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\ ~> S4 rmhist p & ires!p ~= #NotAResult | S5 rmhist p; \
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\ sigma |= S4 rmhist p & ires!p ~= #NotAResult ~> S5 rmhist p; \
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\ sigma |= S5 rmhist p ~> S6 rmhist p |] \
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\ ==> sigma |= S2 rmhist p | S3 rmhist p | S4 rmhist p | S5 rmhist p | S6 rmhist p \
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\ ~> S6 rmhist p"
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(fn _ => [rtac (temp_use LatticeDisjunctionIntro) 1,
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rtac (temp_use LatticeTransitivity) 1, atac 2,
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rtac (S3S4S5S6LeadstoS6 RS (temp_use LatticeTransitivity)) 1,
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auto_tac (MI_css addSIs2 [S3S4S5S6LeadstoS6,necT]
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addIs2 [ImplLeadsto_gen] addsimps2 Init_defs)
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3807
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339 |
]);
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340 |
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qed_goal "NotS1LeadstoS6" MemoryImplementation.thy
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6255
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"!!sigma. [| sigma |= []ImpInv rmhist p; \
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\ sigma |= S2 rmhist p ~> S3 rmhist p; \
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\ sigma |= S3 rmhist p ~> S4 rmhist p | S6 rmhist p; \
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\ sigma |= S4 rmhist p & ires!p = #NotAResult \
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\ ~> S4 rmhist p & ires!p ~= #NotAResult | S5 rmhist p; \
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347 |
\ sigma |= S4 rmhist p & ires!p ~= #NotAResult ~> S5 rmhist p; \
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\ sigma |= S5 rmhist p ~> S6 rmhist p |] \
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\ ==> sigma |= ~S1 rmhist p ~> S6 rmhist p"
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350 |
(fn _ => [rtac (S2S3S4S5S6LeadstoS6 RS (temp_use LatticeTransitivity)) 1,
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351 |
TRYALL atac,
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352 |
etac (temp_use INV_leadsto) 1,
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353 |
rtac (temp_use ImplLeadsto_gen) 1,
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354 |
rtac (temp_use necT) 1,
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355 |
auto_tac (MI_css addsimps2 ImpInv_def::Init_defs addSIs2 [necT])
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3807
|
356 |
]);
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357 |
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358 |
qed_goal "S1Infinite" MemoryImplementation.thy
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6255
|
359 |
"!!sigma. [| sigma |= ~S1 rmhist p ~> S6 rmhist p; \
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360 |
\ sigma |= []<>S6 rmhist p --> []<>S1 rmhist p |] \
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361 |
\ ==> sigma |= []<>S1 rmhist p"
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3807
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362 |
(fn _ => [rtac classical 1,
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6255
|
363 |
asm_full_simp_tac (simpset() addsimps [temp_use NotBox, NotDmd]) 1,
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|
364 |
auto_tac (MI_css addSEs2 [mp,leadsto_infinite] addSDs2 [DBImplBD])
|
3807
|
365 |
]);
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