src/HOL/SMT_Examples/SMT_Examples.certs
changeset 40333 12a06ad29681
parent 40163 a462d5207aa6
child 40681 872b08416fb4
equal deleted inserted replaced
40332:5edeb5d269fa 40333:12a06ad29681
     1 d4b1481d70f20d4d6280999633c905e21d180d13 8 0
     1 24d44e2684a632b0246b194cc850faec2cea7de6 33 0
     2 #2 := false
       
     3 #1 := true
       
     4 #8 := (not true)
       
     5 #26 := (iff #8 false)
       
     6 #27 := [rewrite]: #26
       
     7 #25 := [asserted]: #8
       
     8 [mp #25 #27]: false
       
     9 unsat
       
    10 a38979487be0aafcf2d387180e92dfd3bd43e483 33 0
       
    11 #2 := false
     2 #2 := false
    12 decl f1 :: S1
     3 decl f1 :: S1
    13 #4 := f1
     4 #4 := f1
    14 decl f3 :: S1
     5 decl f3 :: S1
    15 #8 := f3
     6 #8 := f3
    39 #45 := [monotonicity #42]: #44
    30 #45 := [monotonicity #42]: #44
    40 #49 := [trans #45 #47]: #48
    31 #49 := [trans #45 #47]: #48
    41 #29 := [asserted]: #12
    32 #29 := [asserted]: #12
    42 [mp #29 #49]: false
    33 [mp #29 #49]: false
    43 unsat
    34 unsat
    44 fd75276ee28b486a6ea1b6b677d04008959d13f8 37 0
    35 1b7b7e7109fa2efdf94c204be8d611210920badb 8 0
       
    36 #2 := false
       
    37 #1 := true
       
    38 #8 := (not true)
       
    39 #26 := (iff #8 false)
       
    40 #27 := [rewrite]: #26
       
    41 #25 := [asserted]: #8
       
    42 [mp #25 #27]: false
       
    43 unsat
       
    44 10a83d48b539d27c174c61f5874470265d21b40f 37 0
    45 #2 := false
    45 #2 := false
    46 decl f1 :: S1
    46 decl f1 :: S1
    47 #4 := f1
    47 #4 := f1
    48 decl f3 :: S1
    48 decl f3 :: S1
    49 #8 := f3
    49 #8 := f3
    77 #49 := [monotonicity #46]: #48
    77 #49 := [monotonicity #46]: #48
    78 #53 := [trans #49 #51]: #52
    78 #53 := [trans #49 #51]: #52
    79 #29 := [asserted]: #12
    79 #29 := [asserted]: #12
    80 [mp #29 #53]: false
    80 [mp #29 #53]: false
    81 unsat
    81 unsat
    82 58aaefc3b25d8181c01a2139430686aeca861bf3 66 0
    82 060c210941c0fd9eca58c8250fc66d664e976010 66 0
    83 #2 := false
    83 #2 := false
    84 decl f4 :: S1
    84 decl f4 :: S1
    85 #10 := f4
    85 #10 := f4
    86 decl f1 :: S1
    86 decl f1 :: S1
    87 #4 := f1
    87 #4 := f1
   144 #81 := [monotonicity #78 #76]: #80
   144 #81 := [monotonicity #78 #76]: #80
   145 #85 := [trans #81 #83]: #84
   145 #85 := [trans #81 #83]: #84
   146 #71 := [and-elim #69]: #40
   146 #71 := [and-elim #69]: #40
   147 [mp #71 #85]: false
   147 [mp #71 #85]: false
   148 unsat
   148 unsat
   149 a3969d96ad7c1fdd20f7d69abeb13b18bac4be8d 1 0
   149 b0eed80076353895afe2bbf37d588b79cf593079 1 0
   150 unsat
   150 unsat
   151 694292afe609b4087c0435b347aed1c0c0b6b45b 94 0
   151 d37af75fba79a43c8aa95dbef345ea660c999f99 94 0
   152 #2 := false
   152 #2 := false
   153 decl f1 :: S1
   153 decl f1 :: S1
   154 #4 := f1
   154 #4 := f1
   155 decl f3 :: S1
   155 decl f3 :: S1
   156 #8 := f3
   156 #8 := f3
   241 #97 := [monotonicity #94]: #96
   241 #97 := [monotonicity #94]: #96
   242 #108 := [trans #97 #106]: #107
   242 #108 := [trans #97 #106]: #107
   243 #39 := [asserted]: #22
   243 #39 := [asserted]: #22
   244 [mp #39 #108]: false
   244 [mp #39 #108]: false
   245 unsat
   245 unsat
   246 fcb0f1f1909bdd097de1e485a000708289f9f1ed 72 0
   246 b3ee7b71753d028d8ffbc5d42df5f0f79660f6e7 72 0
   247 #2 := false
   247 #2 := false
   248 decl f1 :: S1
   248 decl f1 :: S1
   249 #4 := f1
   249 #4 := f1
   250 decl f3 :: S1
   250 decl f3 :: S1
   251 #8 := f3
   251 #8 := f3
   314 #84 := [monotonicity #81]: #83
   314 #84 := [monotonicity #81]: #83
   315 #88 := [trans #84 #86]: #87
   315 #88 := [trans #84 #86]: #87
   316 #36 := [asserted]: #19
   316 #36 := [asserted]: #19
   317 [mp #36 #88]: false
   317 [mp #36 #88]: false
   318 unsat
   318 unsat
   319 36c95d1da5779fd86d36cb33e0f80e4f14e6c4f0 234 0
   319 b6f4097a3d567e9383135805312389841b9ed5f3 234 0
   320 #2 := false
   320 #2 := false
   321 decl f6 :: S1
   321 decl f6 :: S1
   322 #14 := f6
   322 #14 := f6
   323 decl f1 :: S1
   323 decl f1 :: S1
   324 #4 := f1
   324 #4 := f1
   549 #95 := [trans #90 #93]: #94
   549 #95 := [trans #90 #93]: #94
   550 #69 := [asserted]: #18
   550 #69 := [asserted]: #18
   551 #96 := [mp #69 #95]: #91
   551 #96 := [mp #69 #95]: #91
   552 [mp #96 #299]: false
   552 [mp #96 #299]: false
   553 unsat
   553 unsat
   554 44ca45de077963316e54f5cdfef5cb8cd66ac906 52 0
   554 75e07bc80c3184013212c0a5c60b827b399474ad 52 0
   555 #2 := false
   555 #2 := false
   556 decl f4 :: (-> S2 S2 S2)
   556 decl f4 :: (-> S2 S2 S2)
   557 #16 := (:var 1 S2)
   557 #16 := (:var 1 S2)
   558 #17 := (:var 0 S2)
   558 #17 := (:var 0 S2)
   559 #19 := (f4 #17 #16)
   559 #19 := (f4 #17 #16)
   602 #117 := (not #536)
   602 #117 := (not #536)
   603 #204 := (or #117 #13)
   603 #204 := (or #117 #13)
   604 #118 := [quant-inst]: #204
   604 #118 := [quant-inst]: #204
   605 [unit-resolution #118 #53 #541]: false
   605 [unit-resolution #118 #53 #541]: false
   606 unsat
   606 unsat
   607 f79d03683394ca6e785cbd8e87f4249c3d42307a 2578 0
   607 836f826330ec23da3f93f44a06ef6c00563d7781 2578 0
   608 #2 := false
   608 #2 := false
   609 decl f35 :: S1
   609 decl f35 :: S1
   610 #112 := f35
   610 #112 := f35
   611 decl f1 :: S1
   611 decl f1 :: S1
   612 #4 := f1
   612 #4 := f1
  3181 #3636 := [unit-resolution #1579 #3629]: #1567
  3181 #3636 := [unit-resolution #1579 #3629]: #1567
  3182 #3637 := [unit-resolution #1723 #3632]: #1628
  3182 #3637 := [unit-resolution #1723 #3632]: #1628
  3183 #3638 := [unit-resolution #705 #3637 #3636 #3635]: #683
  3183 #3638 := [unit-resolution #705 #3637 #3636 #3635]: #683
  3184 [unit-resolution #1968 #3638 #3634]: false
  3184 [unit-resolution #1968 #3638 #3634]: false
  3185 unsat
  3185 unsat
  3186 3221f6bae508cb0c6bc508c2b8b4600cdb00669d 95 0
  3186 49266526e51dee0fe0083e5120f86525e2ef1056 95 0
  3187 #2 := false
  3187 #2 := false
  3188 decl f3 :: (-> int S1)
  3188 decl f3 :: (-> int S1)
  3189 decl ?v0!0 :: int
  3189 decl ?v0!0 :: int
  3190 #74 := ?v0!0
  3190 #74 := ?v0!0
  3191 #75 := (f3 ?v0!0)
  3191 #75 := (f3 ?v0!0)
  3277 #114 := [and-elim #101]: #108
  3277 #114 := [and-elim #101]: #108
  3278 #115 := [not-or-elim #114]: #68
  3278 #115 := [not-or-elim #114]: #68
  3279 #102 := [and-elim #101]: #76
  3279 #102 := [and-elim #101]: #76
  3280 [unit-resolution #102 #115]: false
  3280 [unit-resolution #102 #115]: false
  3281 unsat
  3281 unsat
  3282 517d7705593795e4a28f7687bc92edbaaad5e6a6 146 0
  3282 107e72fe657296bfbc7688086b83c6164eff0b08 146 0
  3283 #2 := false
  3283 #2 := false
  3284 decl f3 :: (-> S1 S2 S1)
  3284 decl f3 :: (-> S1 S2 S1)
  3285 #9 := (:var 0 S2)
  3285 #9 := (:var 0 S2)
  3286 decl f4 :: S1
  3286 decl f4 :: S1
  3287 #15 := f4
  3287 #15 := f4
  3424 #596 := (not #615)
  3424 #596 := (not #615)
  3425 #256 := (or #596 #101)
  3425 #256 := (or #596 #101)
  3426 #261 := [quant-inst]: #256
  3426 #261 := [quant-inst]: #256
  3427 [unit-resolution #261 #584 #284]: false
  3427 [unit-resolution #261 #584 #284]: false
  3428 unsat
  3428 unsat
  3429 f7796908cca3a39a93067ec7456dca4edfe09069 146 2
  3429 2bb8a8ad07066951b9c2ff8c6c6ea8a4b3a62bfc 146 2
  3430 #2 := false
  3430 #2 := false
  3431 decl f3 :: (-> S1 S2 S1)
  3431 decl f3 :: (-> S1 S2 S1)
  3432 #9 := (:var 0 S2)
  3432 #9 := (:var 0 S2)
  3433 decl f5 :: S1
  3433 decl f5 :: S1
  3434 #23 := f5
  3434 #23 := f5
  3573 #317 := [quant-inst]: #659
  3573 #317 := [quant-inst]: #659
  3574 [unit-resolution #317 #309 #272]: false
  3574 [unit-resolution #317 #309 #272]: false
  3575 unsat
  3575 unsat
  3576 WARNING: failed to find a pattern for quantifier (quantifier id: k!13)
  3576 WARNING: failed to find a pattern for quantifier (quantifier id: k!13)
  3577 
  3577 
  3578 3d560cfeafa07e8fb4e5aedbf244ed81193a1bdd 91 0
  3578 3415c51851ea95b52ee39d82ddb23d7a42cd9b2f 91 0
  3579 #2 := false
  3579 #2 := false
  3580 decl f3 :: (-> S2 S1)
  3580 decl f3 :: (-> S2 S1)
  3581 decl f4 :: S2
  3581 decl f4 :: S2
  3582 #8 := f4
  3582 #8 := f4
  3583 #9 := (f3 f4)
  3583 #9 := (f3 f4)
  3665 #161 := (not #577)
  3665 #161 := (not #577)
  3666 #248 := (or #161 #70)
  3666 #248 := (or #161 #70)
  3667 #162 := [quant-inst]: #248
  3667 #162 := [quant-inst]: #248
  3668 [unit-resolution #162 #582 #79]: false
  3668 [unit-resolution #162 #582 #79]: false
  3669 unsat
  3669 unsat
  3670 6f4135b5f443c9489ab6f839e6371eb6c05021a1 17 0
  3670 44eecf236b490147dbc51a13ab3759021603fcea 17 0
  3671 #2 := false
  3671 #2 := false
  3672 #8 := 3::int
  3672 #8 := 3::int
  3673 #9 := (= 3::int 3::int)
  3673 #9 := (= 3::int 3::int)
  3674 #10 := (not #9)
  3674 #10 := (not #9)
  3675 #35 := (iff #10 false)
  3675 #35 := (iff #10 false)
  3683 #32 := [monotonicity #29]: #31
  3683 #32 := [monotonicity #29]: #31
  3684 #36 := [trans #32 #34]: #35
  3684 #36 := [trans #32 #34]: #35
  3685 #27 := [asserted]: #10
  3685 #27 := [asserted]: #10
  3686 [mp #27 #36]: false
  3686 [mp #27 #36]: false
  3687 unsat
  3687 unsat
  3688 1fb88686c084cbd29d5379055cf31c165231f0d2 17 0
  3688 f79c070f64eae6123a31ed43ab22ff256427a856 17 0
  3689 #2 := false
  3689 #2 := false
  3690 #8 := 3::real
  3690 #8 := 3::real
  3691 #9 := (= 3::real 3::real)
  3691 #9 := (= 3::real 3::real)
  3692 #10 := (not #9)
  3692 #10 := (not #9)
  3693 #35 := (iff #10 false)
  3693 #35 := (iff #10 false)
  3701 #32 := [monotonicity #29]: #31
  3701 #32 := [monotonicity #29]: #31
  3702 #36 := [trans #32 #34]: #35
  3702 #36 := [trans #32 #34]: #35
  3703 #27 := [asserted]: #10
  3703 #27 := [asserted]: #10
  3704 [mp #27 #36]: false
  3704 [mp #27 #36]: false
  3705 unsat
  3705 unsat
  3706 4439cb9b553ba6a7d3d7adaf0bccb7b403389495 26 0
  3706 4ebfd0cdcde15d352023497277a471fa091558e8 26 0
  3707 #2 := false
  3707 #2 := false
  3708 #11 := 4::int
  3708 #11 := 4::int
  3709 #9 := 1::int
  3709 #9 := 1::int
  3710 #8 := 3::int
  3710 #8 := 3::int
  3711 #10 := (+ 3::int 1::int)
  3711 #10 := (+ 3::int 1::int)
  3728 #41 := [monotonicity #38]: #40
  3728 #41 := [monotonicity #38]: #40
  3729 #45 := [trans #41 #43]: #44
  3729 #45 := [trans #41 #43]: #44
  3730 #30 := [asserted]: #13
  3730 #30 := [asserted]: #13
  3731 [mp #30 #45]: false
  3731 [mp #30 #45]: false
  3732 unsat
  3732 unsat
  3733 f4b4baf086c1953b46b6c8516c9a7e45f6c086ee 41 0
  3733 c45eaaff3b4218ae166b1ee5b57daee45f751625 41 0
  3734 #2 := false
  3734 #2 := false
  3735 decl f3 :: int
  3735 decl f3 :: int
  3736 #8 := f3
  3736 #8 := f3
  3737 decl f5 :: int
  3737 decl f5 :: int
  3738 #10 := f5
  3738 #10 := f5
  3770 #53 := [monotonicity #50]: #52
  3770 #53 := [monotonicity #50]: #52
  3771 #57 := [trans #53 #55]: #56
  3771 #57 := [trans #53 #55]: #56
  3772 #33 := [asserted]: #16
  3772 #33 := [asserted]: #16
  3773 [mp #33 #57]: false
  3773 [mp #33 #57]: false
  3774 unsat
  3774 unsat
  3775 5926d4083f7d2a89c57531d8e87a5d554a39421a 35 0
  3775 c12d97c9fd2930565ac865f67ef562b3c45fbf6a 35 0
  3776 #2 := false
  3776 #2 := false
  3777 #9 := 3::int
  3777 #9 := 3::int
  3778 #10 := 8::int
  3778 #10 := 8::int
  3779 #11 := (<= 3::int 8::int)
  3779 #11 := (<= 3::int 8::int)
  3780 #12 := (ite #11 8::int 3::int)
  3780 #12 := (ite #11 8::int 3::int)
  3806 #52 := [monotonicity #49]: #51
  3806 #52 := [monotonicity #49]: #51
  3807 #56 := [trans #52 #54]: #55
  3807 #56 := [trans #52 #54]: #55
  3808 #31 := [asserted]: #14
  3808 #31 := [asserted]: #14
  3809 [mp #31 #56]: false
  3809 [mp #31 #56]: false
  3810 unsat
  3810 unsat
  3811 53ebe62bcea7dc90158b3082dda2089fed123703 209 0
  3811 7cb5a788981ee8a217912588519fd956ced665e2 209 0
  3812 #2 := false
  3812 #2 := false
  3813 #11 := 0::real
  3813 #11 := 0::real
  3814 decl f4 :: real
  3814 decl f4 :: real
  3815 #9 := f4
  3815 #9 := f4
  3816 #41 := -1::real
  3816 #41 := -1::real
  4016 #229 := [lemma #228]: #93
  4016 #229 := [lemma #228]: #93
  4017 #230 := [unit-resolution #142 #229]: #139
  4017 #230 := [unit-resolution #142 #229]: #139
  4018 #231 := [unit-resolution #159 #230]: #150
  4018 #231 := [unit-resolution #159 #230]: #150
  4019 [th-lemma #125 #220 #227 #231]: false
  4019 [th-lemma #125 #220 #227 #231]: false
  4020 unsat
  4020 unsat
  4021 cbc9c5a04b9570a386fb97f8ff4491630835be54 42 0
  4021 1e234cc93c775a7f92c9808afe1122152dd4b38c 42 0
  4022 #2 := false
  4022 #2 := false
  4023 decl f3 :: (-> S1 S2)
  4023 decl f3 :: (-> S1 S2)
  4024 decl f1 :: S1
  4024 decl f1 :: S1
  4025 #4 := f1
  4025 #4 := f1
  4026 #13 := (f3 f1)
  4026 #13 := (f3 f1)
  4059 #54 := [monotonicity #51]: #53
  4059 #54 := [monotonicity #51]: #53
  4060 #58 := [trans #54 #56]: #57
  4060 #58 := [trans #54 #56]: #57
  4061 #32 := [asserted]: #15
  4061 #32 := [asserted]: #15
  4062 [mp #32 #58]: false
  4062 [mp #32 #58]: false
  4063 unsat
  4063 unsat
  4064 732b399d3ae1d48d68db7a2b4fb14062c7ea7650 54 0
  4064 b18c0c1cf966295783ca6ddab09d2dabebd74ff7 54 0
  4065 #2 := false
  4065 #2 := false
  4066 #13 := 1::int
  4066 #13 := 1::int
  4067 decl f3 :: int
  4067 decl f3 :: int
  4068 #9 := f3
  4068 #9 := f3
  4069 #14 := (< f3 1::int)
  4069 #14 := (< f3 1::int)
  4114 #50 := [monotonicity #47]: #49
  4114 #50 := [monotonicity #47]: #49
  4115 #72 := [trans #50 #70]: #71
  4115 #72 := [trans #50 #70]: #71
  4116 #33 := [asserted]: #16
  4116 #33 := [asserted]: #16
  4117 [mp #33 #72]: false
  4117 [mp #33 #72]: false
  4118 unsat
  4118 unsat
  4119 a511ac5eff75bd85fb28de979615bdeb27073e2f 63 0
  4119 3db1a0441939b3cc14e2a4efb4f74cab6c664bd5 63 0
  4120 #2 := false
  4120 #2 := false
  4121 #15 := 0::int
  4121 #15 := 0::int
  4122 decl f4 :: int
  4122 decl f4 :: int
  4123 #11 := f4
  4123 #11 := f4
  4124 #47 := -1::int
  4124 #47 := -1::int
  4178 #80 := [trans #67 #78]: #79
  4178 #80 := [trans #67 #78]: #79
  4179 #57 := [asserted]: #18
  4179 #57 := [asserted]: #18
  4180 #81 := [mp #57 #80]: #68
  4180 #81 := [mp #57 #80]: #68
  4181 [mp #81 #93]: false
  4181 [mp #81 #93]: false
  4182 unsat
  4182 unsat
  4183 5e99525435673f50d9e2cedb056a3eef3ca48d0f 35 0
  4183 08fc4e7efc68a91cbed93f860a54fb029c71bcbb 35 0
  4184 #2 := false
  4184 #2 := false
  4185 #10 := 5::int
  4185 #10 := 5::int
  4186 #8 := 2::int
  4186 #8 := 2::int
  4187 #9 := (+ 2::int 2::int)
  4187 #9 := (+ 2::int 2::int)
  4188 #11 := (= #9 5::int)
  4188 #11 := (= #9 5::int)
  4214 #50 := [monotonicity #47]: #49
  4214 #50 := [monotonicity #47]: #49
  4215 #54 := [trans #50 #52]: #53
  4215 #54 := [trans #50 #52]: #53
  4216 #30 := [asserted]: #13
  4216 #30 := [asserted]: #13
  4217 [mp #30 #54]: false
  4217 [mp #30 #54]: false
  4218 unsat
  4218 unsat
  4219 cb1ff2dbd74d2844a905d03c2bb5dfdcef7b3703 45 0
  4219 3adb493c0d9d387d1aebf7bcb353d3c00a0851a0 45 0
  4220 #2 := false
  4220 #2 := false
  4221 #15 := 4::real
  4221 #15 := 4::real
  4222 decl f4 :: real
  4222 decl f4 :: real
  4223 #12 := f4
  4223 #12 := f4
  4224 #11 := 7::real
  4224 #11 := 7::real
  4260 #64 := [trans #60 #62]: #63
  4260 #64 := [trans #60 #62]: #63
  4261 #41 := [asserted]: #22
  4261 #41 := [asserted]: #22
  4262 #65 := [mp #41 #64]: #56
  4262 #65 := [mp #41 #64]: #56
  4263 [th-lemma #65 #52 #43]: false
  4263 [th-lemma #65 #52 #43]: false
  4264 unsat
  4264 unsat
  4265 7357ea99a84507698d605d047a8912506786b005 59 0
  4265 5ee51bc5647785432ba0c87ce1c0376c614df467 59 0
  4266 #2 := false
  4266 #2 := false
  4267 #20 := (not false)
  4267 #20 := (not false)
  4268 decl f4 :: int
  4268 decl f4 :: int
  4269 #12 := f4
  4269 #12 := f4
  4270 #8 := 0::int
  4270 #8 := 0::int
  4320 #72 := [monotonicity #69]: #71
  4320 #72 := [monotonicity #69]: #71
  4321 #76 := [trans #72 #74]: #75
  4321 #76 := [trans #72 #74]: #75
  4322 #39 := [asserted]: #22
  4322 #39 := [asserted]: #22
  4323 [mp #39 #76]: false
  4323 [mp #39 #76]: false
  4324 unsat
  4324 unsat
  4325 a2e7fe792ce7e828740707e47e962b9013bfaa8c 43 0
  4325 28a095b5ca08adc7ff0222dfacd76cf43a8ba449 43 0
  4326 #2 := false
  4326 #2 := false
  4327 decl f3 :: int
  4327 decl f3 :: int
  4328 #8 := f3
  4328 #8 := f3
  4329 #9 := 3::int
  4329 #9 := 3::int
  4330 #11 := (<= 3::int f3)
  4330 #11 := (<= 3::int f3)
  4364 #47 := [trans #43 #45]: #46
  4364 #47 := [trans #43 #45]: #46
  4365 #62 := [trans #47 #60]: #61
  4365 #62 := [trans #47 #60]: #61
  4366 #31 := [asserted]: #14
  4366 #31 := [asserted]: #14
  4367 [mp #31 #62]: false
  4367 [mp #31 #62]: false
  4368 unsat
  4368 unsat
  4369 f746fa8e8060fa7d6624d49afb6c22d0c2467190 86 0
  4369 d13adc55a1937ef83f29c016ef8623fe1fda09eb 86 0
  4370 #2 := false
  4370 #2 := false
  4371 decl f3 :: int
  4371 decl f3 :: int
  4372 #9 := f3
  4372 #9 := f3
  4373 #11 := 2::int
  4373 #11 := 2::int
  4374 #34 := (* 2::int f3)
  4374 #34 := (* 2::int f3)
  4451 #81 := (or #59 #63 #65 #61)
  4451 #81 := (or #59 #63 #65 #61)
  4452 #82 := [def-axiom]: #81
  4452 #82 := [def-axiom]: #81
  4453 #104 := [unit-resolution #82 #103 #96 #87]: #65
  4453 #104 := [unit-resolution #82 #103 #96 #87]: #65
  4454 [unit-resolution #104 #117]: false
  4454 [unit-resolution #104 #117]: false
  4455 unsat
  4455 unsat
  4456 96de0a1de3d9897dfb99656d5dd83bfdb80fa75e 551 0
  4456 372a6ad969cb318322945cf566c5d0dc9eaab120 551 0
  4457 #2 := false
  4457 #2 := false
  4458 #174 := 0::int
  4458 #174 := 0::int
  4459 decl f4 :: int
  4459 decl f4 :: int
  4460 #9 := f4
  4460 #9 := f4
  4461 #171 := -1::int
  4461 #171 := -1::int
  5003 #354 := [not-or-elim #352]: #353
  5003 #354 := [not-or-elim #352]: #353
  5004 #411 := [mp #354 #410]: #422
  5004 #411 := [mp #354 #410]: #422
  5005 #617 := [unit-resolution #411 #614]: #421
  5005 #617 := [unit-resolution #411 #614]: #421
  5006 [unit-resolution #601 #617 #593 #616]: false
  5006 [unit-resolution #601 #617 #593 #616]: false
  5007 unsat
  5007 unsat
  5008 be4350e057381018abf4a5df1b96e44aa5440970 2109 0
  5008 79f1383c7c06e3e99fb5b45b946ee8edd0a67644 2109 0
  5009 #2 := false
  5009 #2 := false
  5010 #10 := 0::int
  5010 #10 := 0::int
  5011 decl f3 :: int
  5011 decl f3 :: int
  5012 #8 := f3
  5012 #8 := f3
  5013 #95 := -1::int
  5013 #95 := -1::int
  7113 #2116 := [unit-resolution #1311 #1953]: #2115
  7113 #2116 := [unit-resolution #1311 #1953]: #2115
  7114 #2118 := [unit-resolution #2116 #1624 #1929 #1826 #2016 #1851]: #2117
  7114 #2118 := [unit-resolution #2116 #1624 #1929 #1826 #2016 #1851]: #2117
  7115 #2119 := [unit-resolution #2118 #2109 #2056 #2114 #2113 #2112 #2096 #2108]: #945
  7115 #2119 := [unit-resolution #2118 #2109 #2056 #2114 #2113 #2112 #2096 #2108]: #945
  7116 [unit-resolution #1969 #2119 #2109 #2096 #2042 #2105 #2108]: false
  7116 [unit-resolution #1969 #2119 #2109 #2096 #2042 #2105 #2108]: false
  7117 unsat
  7117 unsat
  7118 9371d51a82e0a1300620d46b4e7e3f2e34923066 52 0
  7118 e5059b0c3e879c6b6b3ce8026895b93ab92e0728 52 0
  7119 #2 := false
  7119 #2 := false
  7120 #12 := 1::real
  7120 #12 := 1::real
  7121 decl f3 :: real
  7121 decl f3 :: real
  7122 #8 := f3
  7122 #8 := f3
  7123 #10 := 2::real
  7123 #10 := 2::real
  7166 #59 := [monotonicity #56]: #58
  7166 #59 := [monotonicity #56]: #58
  7167 #70 := [trans #59 #68]: #69
  7167 #70 := [trans #59 #68]: #69
  7168 #34 := [asserted]: #17
  7168 #34 := [asserted]: #17
  7169 [mp #34 #70]: false
  7169 [mp #34 #70]: false
  7170 unsat
  7170 unsat
  7171 7d808a299ec3aa6543955e0b52da2db4f14e2ebc 348 0
  7171 58d0d0a0a699999905091a630166f1e00b881d19 348 0
  7172 #2 := false
  7172 #2 := false
  7173 #11 := 0::int
  7173 #11 := 0::int
  7174 decl f5 :: int
  7174 decl f5 :: int
  7175 #38 := f5
  7175 #38 := f5
  7176 #421 := (>= f5 0::int)
  7176 #421 := (>= f5 0::int)
  7515 #641 := (or #766 #755 #411)
  7515 #641 := (or #766 #755 #411)
  7516 #642 := [th-lemma]: #641
  7516 #642 := [th-lemma]: #641
  7517 #638 := [unit-resolution #642 #647]: #643
  7517 #638 := [unit-resolution #642 #647]: #643
  7518 [unit-resolution #638 #640 #637]: false
  7518 [unit-resolution #638 #640 #637]: false
  7519 unsat
  7519 unsat
  7520 a58c3bad13ae6ef8848c31ae2ecb4d141ea9bdc6 354 0
  7520 4fc7df80f9cc116a2a88bcb88017dc9b0c75f7fc 354 0
  7521 #2 := false
  7521 #2 := false
  7522 #11 := 0::int
  7522 #11 := 0::int
  7523 decl f5 :: int
  7523 decl f5 :: int
  7524 #38 := f5
  7524 #38 := f5
  7525 #444 := (<= f5 0::int)
  7525 #444 := (<= f5 0::int)
  7870 #620 := (or #761 #749 #406)
  7870 #620 := (or #761 #749 #406)
  7871 #621 := [th-lemma]: #620
  7871 #621 := [th-lemma]: #620
  7872 #626 := [unit-resolution #621 #634]: #753
  7872 #626 := [unit-resolution #621 #634]: #753
  7873 [unit-resolution #626 #619 #508]: false
  7873 [unit-resolution #626 #619 #508]: false
  7874 unsat
  7874 unsat
  7875 cfd6420dc9709ceb6bf8be602fb4605c1ddb5222 101 0
  7875 391853aefaeecebad29422aff20420b5c8400b71 101 0
  7876 #2 := false
  7876 #2 := false
  7877 #9 := 0::real
  7877 #9 := 0::real
  7878 decl f3 :: real
  7878 decl f3 :: real
  7879 #8 := f3
  7879 #8 := f3
  7880 #10 := (= f3 0::real)
  7880 #10 := (= f3 0::real)
  7972 #117 := (not #99)
  7972 #117 := (not #99)
  7973 #119 := (or #10 #117 #118)
  7973 #119 := (or #10 #117 #118)
  7974 #120 := [th-lemma]: #119
  7974 #120 := [th-lemma]: #119
  7975 [unit-resolution #120 #116 #109 #43]: false
  7975 [unit-resolution #120 #116 #109 #43]: false
  7976 unsat
  7976 unsat
  7977 957b603c67e0eb51df6576d5eeddcc6aa6ccd469 943 0
  7977 fee0ab8e0ed90b0d56c8dc3103c9526d6f1496af 943 0
  7978 #2 := false
  7978 #2 := false
  7979 #49 := 1::int
  7979 #49 := 1::int
  7980 decl f4 :: (-> int int int)
  7980 decl f4 :: (-> int int int)
  7981 #41 := 2::int
  7981 #41 := 2::int
  7982 decl f6 :: int
  7982 decl f6 :: int
  8916 #1292 := [unit-resolution #1245 #1291 #1290]: #407
  8916 #1292 := [unit-resolution #1245 #1291 #1290]: #407
  8917 #1293 := [unit-resolution #1185 #1289]: #473
  8917 #1293 := [unit-resolution #1185 #1289]: #473
  8918 #1294 := [unit-resolution #1107 #1293 #1239]: #405
  8918 #1294 := [unit-resolution #1107 #1293 #1239]: #405
  8919 [unit-resolution #1252 #1294 #1292]: false
  8919 [unit-resolution #1252 #1294 #1292]: false
  8920 unsat
  8920 unsat
  8921 e0bd8674b0a8871e3484c1aaf5e9760d6cdde8fa 24 0
  8921 a36cefa1a79f7b6b132d839263e2dbea9c7e87fc 24 0
  8922 #2 := false
  8922 #2 := false
  8923 #8 := (exists (vars (?v0 int)) false)
  8923 #8 := (exists (vars (?v0 int)) false)
  8924 #9 := (not #8)
  8924 #9 := (not #8)
  8925 #10 := (not #9)
  8925 #10 := (not #9)
  8926 #42 := (iff #10 false)
  8926 #42 := (iff #10 false)
  8941 #39 := [monotonicity #36]: #38
  8941 #39 := [monotonicity #36]: #38
  8942 #43 := [trans #39 #41]: #42
  8942 #43 := [trans #39 #41]: #42
  8943 #27 := [asserted]: #10
  8943 #27 := [asserted]: #10
  8944 [mp #27 #43]: false
  8944 [mp #27 #43]: false
  8945 unsat
  8945 unsat
  8946 20e7b35733689b5c0fe416fc2b22bfe44b252442 24 0
  8946 54fcba387e363cf8083d4867a9793bbccb7a0314 24 0
  8947 #2 := false
  8947 #2 := false
  8948 #8 := (exists (vars (?v0 real)) false)
  8948 #8 := (exists (vars (?v0 real)) false)
  8949 #9 := (not #8)
  8949 #9 := (not #8)
  8950 #10 := (not #9)
  8950 #10 := (not #9)
  8951 #42 := (iff #10 false)
  8951 #42 := (iff #10 false)
  8966 #39 := [monotonicity #36]: #38
  8966 #39 := [monotonicity #36]: #38
  8967 #43 := [trans #39 #41]: #42
  8967 #43 := [trans #39 #41]: #42
  8968 #27 := [asserted]: #10
  8968 #27 := [asserted]: #10
  8969 [mp #27 #43]: false
  8969 [mp #27 #43]: false
  8970 unsat
  8970 unsat
  8971 c605fee711b129b0bde66fbd9b8f8cc9ce226e9a 1 0
  8971 fb9fab32fe487ed4f4e3d6fe3002d02a0faf856f 1 0
  8972 unsat
  8972 unsat
  8973 e58017e3173d9778bc4b43bd6c7d6554fa96991e 1 0
  8973 04a6b607d97a19c61cf9fb86541a5de438beb133 1 0
  8974 unsat
  8974 unsat
  8975 0e0dcf19cd5b120a9f262cfa9c01b662a315ee94 1 0
  8975 12094d1935a50c8a07214f044f89a779adda7144 1 0
  8976 unsat
  8976 unsat
  8977 1781c1a480d6415ddb235a621259ce2092732ba5 67 0
  8977 5e524c2f74a70173d25f03f6292e4c1715c27295 67 0
  8978 #2 := false
  8978 #2 := false
  8979 #9 := 0::int
  8979 #9 := 0::int
  8980 #12 := 1::int
  8980 #12 := 1::int
  8981 #142 := (= 1::int 0::int)
  8981 #142 := (= 1::int 0::int)
  8982 #144 := (iff #142 false)
  8982 #144 := (iff #142 false)
  9040 #139 := [symm #81]: #138
  9040 #139 := [symm #81]: #138
  9041 #141 := [trans #139 #82]: #140
  9041 #141 := [trans #139 #82]: #140
  9042 #143 := [trans #141 #80]: #142
  9042 #143 := [trans #141 #80]: #142
  9043 [mp #143 #145]: false
  9043 [mp #143 #145]: false
  9044 unsat
  9044 unsat
  9045 cb54bc1c8221ce33a204ef4756c350ab3a9165fd 82 0
  9045 8d9412b39d1e4ff552ff059a2a38b571d1cc91d5 82 0
  9046 #2 := false
  9046 #2 := false
  9047 #9 := (:var 0 int)
  9047 #9 := (:var 0 int)
  9048 #11 := 0::int
  9048 #11 := 0::int
  9049 #13 := (<= 0::int #9)
  9049 #13 := (<= 0::int #9)
  9050 #12 := (< #9 0::int)
  9050 #12 := (< #9 0::int)
  9123 #48 := [monotonicity #45]: #47
  9123 #48 := [monotonicity #45]: #47
  9124 #101 := [trans #48 #99]: #100
  9124 #101 := [trans #48 #99]: #100
  9125 #35 := [asserted]: #18
  9125 #35 := [asserted]: #18
  9126 [mp #35 #101]: false
  9126 [mp #35 #101]: false
  9127 unsat
  9127 unsat
  9128 05e26467c63b2926bb1206f4d9498749ac8572cd 78 0
  9128 27ab42ad2d8b0d1fd722c36b1b4da113e0100061 78 0
  9129 #2 := false
  9129 #2 := false
  9130 #9 := (:var 0 int)
  9130 #9 := (:var 0 int)
  9131 #11 := 2::int
  9131 #11 := 2::int
  9132 #15 := (* 2::int #9)
  9132 #15 := (* 2::int #9)
  9133 #13 := 1::int
  9133 #13 := 1::int
  9202 #57 := [monotonicity #54]: #56
  9202 #57 := [monotonicity #54]: #56
  9203 #97 := [trans #57 #95]: #96
  9203 #97 := [trans #57 #95]: #96
  9204 #36 := [asserted]: #19
  9204 #36 := [asserted]: #19
  9205 [mp #36 #97]: false
  9205 [mp #36 #97]: false
  9206 unsat
  9206 unsat
  9207 9a25b8cd095131859f14e6e15166f75f654f8b36 61 0
  9207 df217f217128f3754a777d8b086332e1f6ca39ed 61 0
  9208 #2 := false
  9208 #2 := false
  9209 #13 := (:var 0 int)
  9209 #13 := (:var 0 int)
  9210 #8 := 2::int
  9210 #8 := 2::int
  9211 #14 := (* 2::int #13)
  9211 #14 := (* 2::int #13)
  9212 #11 := 1::int
  9212 #11 := 1::int
  9264 #55 := [monotonicity #52]: #54
  9264 #55 := [monotonicity #52]: #54
  9265 #80 := [trans #55 #78]: #79
  9265 #80 := [trans #55 #78]: #79
  9266 #35 := [asserted]: #18
  9266 #35 := [asserted]: #18
  9267 [mp #35 #80]: false
  9267 [mp #35 #80]: false
  9268 unsat
  9268 unsat
  9269 b845be4ad91437fd7de4e1e43e09de89dff87060 111 0
  9269 ae3d6219d877e775dfed10c63209e257accf66b7 111 0
  9270 #2 := false
  9270 #2 := false
  9271 #8 := 2::int
  9271 #8 := 2::int
  9272 decl ?v0!1 :: int
  9272 decl ?v0!1 :: int
  9273 #92 := ?v0!1
  9273 #92 := ?v0!1
  9274 decl ?v1!0 :: int
  9274 decl ?v1!0 :: int
  9376 #132 := [not-or-elim #104]: #118
  9376 #132 := [not-or-elim #104]: #118
  9377 #188 := (or #109 #121 #115)
  9377 #188 := (or #109 #121 #115)
  9378 #189 := [th-lemma]: #188
  9378 #189 := [th-lemma]: #188
  9379 [unit-resolution #189 #132 #130 #131]: false
  9379 [unit-resolution #189 #132 #130 #131]: false
  9380 unsat
  9380 unsat
  9381 d516d2245b3e1198319c778f5d87f60364d9480b 89 0
  9381 13bee6926c3836fd51ee6bc754d5c22e812fc512 89 0
  9382 #2 := false
  9382 #2 := false
  9383 #8 := 0::int
  9383 #8 := 0::int
  9384 decl ?v0!0 :: int
  9384 decl ?v0!0 :: int
  9385 #85 := ?v0!0
  9385 #85 := ?v0!0
  9386 #80 := (<= ?v0!0 0::int)
  9386 #80 := (<= ?v0!0 0::int)
  9466 #156 := (or #89 #151 #88)
  9466 #156 := (or #89 #151 #88)
  9467 #157 := [def-axiom]: #156
  9467 #157 := [def-axiom]: #156
  9468 #172 := [unit-resolution #157 #95]: #171
  9468 #172 := [unit-resolution #157 #95]: #171
  9469 [unit-resolution #172 #170 #167]: false
  9469 [unit-resolution #172 #170 #167]: false
  9470 unsat
  9470 unsat
  9471 16973ba3459b683ba763cfd9d1b131b50880d52b 83 2
  9471 d8021ae1b4589558d9fd489bf446659dddb6bd92 83 2
  9472 #2 := false
  9472 #2 := false
  9473 #9 := 0::int
  9473 #9 := 0::int
  9474 #8 := (:var 0 int)
  9474 #8 := (:var 0 int)
  9475 #47 := (<= #8 0::int)
  9475 #47 := (<= #8 0::int)
  9476 #48 := (not #47)
  9476 #48 := (not #47)
  9552 #62 := [mp~ #59 #68]: #54
  9552 #62 := [mp~ #59 #68]: #54
  9553 [unit-resolution #62 #179]: false
  9553 [unit-resolution #62 #179]: false
  9554 unsat
  9554 unsat
  9555 WARNING: failed to find a pattern for quantifier (quantifier id: k!9)
  9555 WARNING: failed to find a pattern for quantifier (quantifier id: k!9)
  9556 
  9556 
  9557 6a2477ce7e396f5a6b8350494c34556e3187382b 180 2
  9557 d2e44415b02dc3e73faa264730b98a3e42a2c4b7 180 2
  9558 #2 := false
  9558 #2 := false
  9559 #16 := 3::int
  9559 #16 := 3::int
  9560 #37 := -1::int
  9560 #37 := -1::int
  9561 decl z3name!0 :: bool
  9561 decl z3name!0 :: bool
  9562 #90 := z3name!0
  9562 #90 := z3name!0
  9735 #586 := [th-lemma]: #312
  9735 #586 := [th-lemma]: #312
  9736 [unit-resolution #586 #589 #212]: false
  9736 [unit-resolution #586 #589 #212]: false
  9737 unsat
  9737 unsat
  9738 WARNING: failed to find a pattern for quantifier (quantifier id: k!9)
  9738 WARNING: failed to find a pattern for quantifier (quantifier id: k!9)
  9739 
  9739 
  9740 2c2ba5876a1ae5b4aacba3ec088a92e8517d1db5 68 0
  9740 4b7d931172988b3d273106901290917cf166502b 68 0
  9741 #2 := false
  9741 #2 := false
  9742 #16 := 1::int
  9742 #16 := 1::int
  9743 #13 := (:var 1 int)
  9743 #13 := (:var 1 int)
  9744 #11 := 6::int
  9744 #11 := 6::int
  9745 #12 := (- 6::int)
  9745 #12 := (- 6::int)
  9804 #77 := [trans #73 #75]: #76
  9804 #77 := [trans #73 #75]: #76
  9805 #88 := [trans #77 #86]: #87
  9805 #88 := [trans #77 #86]: #87
  9806 #37 := [asserted]: #20
  9806 #37 := [asserted]: #20
  9807 [mp #37 #88]: false
  9807 [mp #37 #88]: false
  9808 unsat
  9808 unsat
  9809 3bc68a4890101c78401460850d978a5b784ef891 107 0
  9809 3bad73f4a46430e1cd795e36a5d12f24c1d02fca 107 0
  9810 #2 := false
  9810 #2 := false
  9811 #8 := 0::int
  9811 #8 := 0::int
  9812 decl ?v1!1 :: int
  9812 decl ?v1!1 :: int
  9813 #90 := ?v1!1
  9813 #90 := ?v1!1
  9814 decl ?v2!0 :: int
  9814 decl ?v2!0 :: int
  9912 #106 := [not-or-elim #105]: #107
  9912 #106 := [not-or-elim #105]: #107
  9913 #129 := [and-elim #106]: #95
  9913 #129 := [and-elim #106]: #95
  9914 #128 := [and-elim #106]: #93
  9914 #128 := [and-elim #106]: #93
  9915 [th-lemma #128 #129 #130]: false
  9915 [th-lemma #128 #129 #130]: false
  9916 unsat
  9916 unsat
  9917 69398382e4236c1f3e9ea09ef96d5056d4f3fa6e 117 0
  9917 87d0780ec63c3625f21f826c074cd13be4d62e3f 117 0
  9918 #2 := false
  9918 #2 := false
  9919 #8 := 0::int
  9919 #8 := 0::int
  9920 decl ?v1!1 :: int
  9920 decl ?v1!1 :: int
  9921 #100 := ?v1!1
  9921 #100 := ?v1!1
  9922 #103 := (<= ?v1!1 0::int)
  9922 #103 := (<= ?v1!1 0::int)
 10030 #191 := (or #96 #103)
 10030 #191 := (or #96 #103)
 10031 #192 := [th-lemma]: #191
 10031 #192 := [th-lemma]: #191
 10032 #193 := [unit-resolution #192 #115]: #103
 10032 #193 := [unit-resolution #192 #115]: #103
 10033 [unit-resolution #193 #135]: false
 10033 [unit-resolution #193 #135]: false
 10034 unsat
 10034 unsat
 10035 4e8319ba61c4c37d1677e9a262b47203f2bf5468 148 0
 10035 8cf44aadad8c0d87f2f57333fcb342b5ab385732 148 0
 10036 #2 := false
 10036 #2 := false
 10037 #149 := (not false)
 10037 #149 := (not false)
 10038 #11 := 0::int
 10038 #11 := 0::int
 10039 #9 := (:var 0 int)
 10039 #9 := (:var 0 int)
 10040 #57 := (<= #9 0::int)
 10040 #57 := (<= #9 0::int)
 10179 #117 := [mp #116 #126]: #124
 10179 #117 := [mp #116 #126]: #124
 10180 #131 := [mp #117 #130]: #128
 10180 #131 := [mp #117 #130]: #128
 10181 #163 := [mp #131 #162]: #158
 10181 #163 := [mp #131 #162]: #158
 10182 [mp #163 #186]: false
 10182 [mp #163 #186]: false
 10183 unsat
 10183 unsat
 10184 a21b19aa84de923d8a0d2dc0af8016cd64248558 67 0
 10184 505b296c347b1d80912f4657132db5ad5ac9be4f 67 0
 10185 #2 := false
 10185 #2 := false
 10186 #8 := (:var 0 int)
 10186 #8 := (:var 0 int)
 10187 #9 := (pattern #8)
 10187 #9 := (pattern #8)
 10188 decl f3 :: int
 10188 decl f3 :: int
 10189 #10 := f3
 10189 #10 := f3
 10247 #45 := [monotonicity #42]: #44
 10247 #45 := [monotonicity #42]: #44
 10248 #85 := [trans #45 #83]: #84
 10248 #85 := [trans #45 #83]: #84
 10249 #35 := [asserted]: #18
 10249 #35 := [asserted]: #18
 10250 [mp #35 #85]: false
 10250 [mp #35 #85]: false
 10251 unsat
 10251 unsat
 10252 53ac944328a76df2270bb4117390a226d92d4e8d 1 0
 10252 69b5f9a8c6931a47249060824265e608f534018d 1 0
 10253 unsat
 10253 unsat
 10254 80d97536e18b652f6d95d83165f7e113fa8206dd 75 0
 10254 153386649b53dd5f988fd1bc7b72bcd290f53da9 75 0
 10255 #2 := false
 10255 #2 := false
 10256 #10 := 1::int
 10256 #10 := 1::int
 10257 decl f5 :: int
 10257 decl f5 :: int
 10258 #12 := f5
 10258 #12 := f5
 10259 #16 := (+ f5 1::int)
 10259 #16 := (+ f5 1::int)
 10325 #87 := [monotonicity #84]: #86
 10325 #87 := [monotonicity #84]: #86
 10326 #91 := [trans #87 #89]: #90
 10326 #91 := [trans #87 #89]: #90
 10327 #37 := [asserted]: #20
 10327 #37 := [asserted]: #20
 10328 [mp #37 #91]: false
 10328 [mp #37 #91]: false
 10329 unsat
 10329 unsat
 10330 1290567b7974f50913459a9370404d1fb27c5c04 62 0
 10330 68a3071b380f0f7c03304499d1f2835f0bf361c3 62 0
 10331 #2 := false
 10331 #2 := false
 10332 decl f4 :: real
 10332 decl f4 :: real
 10333 #10 := f4
 10333 #10 := f4
 10334 decl f3 :: real
 10334 decl f3 :: real
 10335 #8 := f3
 10335 #8 := f3
 10388 #75 := [monotonicity #72]: #74
 10388 #75 := [monotonicity #72]: #74
 10389 #79 := [trans #75 #77]: #78
 10389 #79 := [trans #75 #77]: #78
 10390 #37 := [asserted]: #20
 10390 #37 := [asserted]: #20
 10391 [mp #37 #79]: false
 10391 [mp #37 #79]: false
 10392 unsat
 10392 unsat
 10393 539e99c284f7a3ed7bb350da08f51bfa73f9e832 141 0
 10393 b6399504e06b7554863175061a53aa7486cc9086 141 0
 10394 #2 := false
 10394 #2 := false
 10395 decl f6 :: int
 10395 decl f6 :: int
 10396 #13 := f6
 10396 #13 := f6
 10397 decl f7 :: int
 10397 decl f7 :: int
 10398 #17 := f7
 10398 #17 := f7
 10530 #151 := [monotonicity #148]: #150
 10530 #151 := [monotonicity #148]: #150
 10531 #155 := [trans #151 #153]: #154
 10531 #155 := [trans #151 #153]: #154
 10532 #50 := [asserted]: #33
 10532 #50 := [asserted]: #33
 10533 [mp #50 #155]: false
 10533 [mp #50 #155]: false
 10534 unsat
 10534 unsat
 10535 95f708529404688f5c32519f5db83b1972672eb0 252 0
 10535 161d4df3b39a91bf1bc07402c22e85ffba8398b2 252 0
 10536 #2 := false
 10536 #2 := false
 10537 #13 := 0::int
 10537 #13 := 0::int
 10538 decl f4 :: (-> S2 int)
 10538 decl f4 :: (-> S2 int)
 10539 decl f3 :: (-> int S2)
 10539 decl f3 :: (-> int S2)
 10540 decl f5 :: S2
 10540 decl f5 :: S2
 10783 #543 := (or #458 #562)
 10783 #543 := (or #458 #562)
 10784 #537 := [th-lemma]: #543
 10784 #537 := [th-lemma]: #543
 10785 #544 := [unit-resolution #537 #456]: #562
 10785 #544 := [unit-resolution #537 #456]: #562
 10786 [th-lemma #460 #544 #542 #551]: false
 10786 [th-lemma #460 #544 #542 #551]: false
 10787 unsat
 10787 unsat
 10788 069a886d4e32ad09f893e803be1b967f3568fe31 227 0
 10788 2eacc8bb83fecb0fe81d96fc93fc64a7d11a9e4d 227 0
 10789 #2 := false
 10789 #2 := false
 10790 #27 := 3::int
 10790 #27 := 3::int
 10791 decl f4 :: (-> S2 int)
 10791 decl f4 :: (-> S2 int)
 10792 decl f5 :: S2
 10792 decl f5 :: S2
 10793 #25 := f5
 10793 #25 := f5
 11011 #601 := (or #606 #632)
 11011 #601 := (or #606 #632)
 11012 #602 := [th-lemma]: #601
 11012 #602 := [th-lemma]: #601
 11013 #607 := [unit-resolution #602 #605]: #632
 11013 #607 := [unit-resolution #602 #605]: #632
 11014 [th-lemma #161 #607 #160]: false
 11014 [th-lemma #161 #607 #160]: false
 11015 unsat
 11015 unsat
 11016 dc0cfb9f55d790de5cad944289080b012df32109 367 0
 11016 61d261a95e60947f23f698475332084ad9cfd094 367 0
 11017 #2 := false
 11017 #2 := false
 11018 #13 := 0::int
 11018 #13 := 0::int
 11019 decl f4 :: (-> S2 int)
 11019 decl f4 :: (-> S2 int)
 11020 decl f5 :: S2
 11020 decl f5 :: S2
 11021 #26 := f5
 11021 #26 := f5
 11379 #458 := (not #474)
 11379 #458 := (not #474)
 11380 #460 := (or #458 #561)
 11380 #460 := (or #458 #561)
 11381 #461 := [th-lemma]: #460
 11381 #461 := [th-lemma]: #460
 11382 [unit-resolution #461 #469 #457]: false
 11382 [unit-resolution #461 #469 #457]: false
 11383 unsat
 11383 unsat
 11384 1119baa29d78de9d8299759a1e2778fd64cb45ac 299 0
 11384 ddf1adc32377020a68931e791f8d3bc93a479493 299 0
 11385 #2 := false
 11385 #2 := false
 11386 #13 := 0::int
 11386 #13 := 0::int
 11387 decl f4 :: (-> S2 int)
 11387 decl f4 :: (-> S2 int)
 11388 decl f3 :: (-> int S2)
 11388 decl f3 :: (-> int S2)
 11389 decl f5 :: S2
 11389 decl f5 :: S2
 11679 #612 := (or #616 #685)
 11679 #612 := (or #616 #685)
 11680 #617 := [th-lemma]: #612
 11680 #617 := [th-lemma]: #612
 11681 #603 := [unit-resolution #617 #615]: #685
 11681 #603 := [unit-resolution #617 #615]: #685
 11682 [th-lemma #625 #190 #603 #630]: false
 11682 [th-lemma #625 #190 #603 #630]: false
 11683 unsat
 11683 unsat
 11684 bc26a0abfecc650600742f8182ea35bd8e9c0657 458 0
 11684 044639db28fa915f30475668c634e5237efaa068 458 0
 11685 #2 := false
 11685 #2 := false
 11686 #13 := 0::int
 11686 #13 := 0::int
 11687 decl f4 :: (-> S2 int)
 11687 decl f4 :: (-> S2 int)
 11688 decl f3 :: (-> int S2)
 11688 decl f3 :: (-> int S2)
 11689 decl f5 :: S2
 11689 decl f5 :: S2
 12138 #364 := (or #373 #625)
 12138 #364 := (or #373 #625)
 12139 #374 := [th-lemma]: #364
 12139 #374 := [th-lemma]: #364
 12140 #355 := [unit-resolution #374 #372]: #373
 12140 #355 := [unit-resolution #374 #372]: #373
 12141 [unit-resolution #355 #328]: false
 12141 [unit-resolution #355 #328]: false
 12142 unsat
 12142 unsat
 12143 d28cb53d0b19f6ffbd9f6906e69a9e4028ab5365 161 0
 12143 35a0968e29848376b1a21560a270f15f6d19aed4 161 0
 12144 #2 := false
 12144 #2 := false
 12145 #13 := 0::int
 12145 #13 := 0::int
 12146 decl f5 :: int
 12146 decl f5 :: int
 12147 #25 := f5
 12147 #25 := f5
 12148 #135 := -1::int
 12148 #135 := -1::int
 12300 #643 := (or #652 #278)
 12300 #643 := (or #652 #278)
 12301 #644 := [th-lemma]: #643
 12301 #644 := [th-lemma]: #643
 12302 #366 := [unit-resolution #644 #660]: #652
 12302 #366 := [unit-resolution #644 #660]: #652
 12303 [th-lemma #661 #366 #266]: false
 12303 [th-lemma #661 #366 #266]: false
 12304 unsat
 12304 unsat
 12305 3bdd721710ce740508c48327f8e9174f1a8cdb9c 604 0
 12305 30478456884b028b09fee79763641a90a5f3dc95 604 0
 12306 #2 := false
 12306 #2 := false
 12307 #13 := 0::int
 12307 #13 := 0::int
 12308 decl f4 :: (-> S2 int)
 12308 decl f4 :: (-> S2 int)
 12309 decl f3 :: (-> int S2)
 12309 decl f3 :: (-> int S2)
 12310 decl f7 :: S2
 12310 decl f7 :: S2
 12905 #601 := [quant-inst]: #597
 12905 #601 := [quant-inst]: #597
 12906 #599 := [mp #601 #598]: #594
 12906 #599 := [mp #601 #598]: #594
 12907 #1005 := [unit-resolution #599 #859]: #455
 12907 #1005 := [unit-resolution #599 #859]: #455
 12908 [unit-resolution #1005 #1004 #994]: false
 12908 [unit-resolution #1005 #1004 #994]: false
 12909 unsat
 12909 unsat
 12910 9702672d0e4ef4f07fbabb8ea1413e6a7036c6b3 61 0
 12910 b7294e8991937b94c2eeb87ee3638d9d5f007d01 61 0
 12911 #2 := false
 12911 #2 := false
 12912 decl f7 :: S3
 12912 decl f7 :: S3
 12913 #12 := f7
 12913 #12 := f7
 12914 decl f5 :: S3
 12914 decl f5 :: S3
 12915 #8 := f5
 12915 #8 := f5
 12967 #251 := [trans #247 #56]: #14
 12967 #251 := [trans #247 #56]: #14
 12968 #57 := (not #14)
 12968 #57 := (not #14)
 12969 #59 := [not-or-elim #58]: #57
 12969 #59 := [not-or-elim #58]: #57
 12970 [unit-resolution #59 #251]: false
 12970 [unit-resolution #59 #251]: false
 12971 unsat
 12971 unsat
 12972 eb96c266a8e3d434df367635dd7c28e36177b61a 116 0
 12972 0eb592b66cd32b0b3c146dc31bf114d3abca5113 116 0
 12973 #2 := false
 12973 #2 := false
 12974 decl f10 :: (-> S5 S3)
 12974 decl f10 :: (-> S5 S3)
 12975 decl f7 :: S5
 12975 decl f7 :: S5
 12976 #13 := f7
 12976 #13 := f7
 12977 #18 := (f10 f7)
 12977 #18 := (f10 f7)
 13084 #612 := [trans #617 #613]: #19
 13084 #612 := [trans #617 #613]: #19
 13085 #80 := (not #19)
 13085 #80 := (not #19)
 13086 #81 := [not-or-elim #78]: #80
 13086 #81 := [not-or-elim #78]: #80
 13087 [unit-resolution #81 #612]: false
 13087 [unit-resolution #81 #612]: false
 13088 unsat
 13088 unsat
 13089 9aa5c4fb11199431a576a38868b15130e8351add 192 0
 13089 919519ba12504066a1609e5f376b9f35de340ebd 192 0
 13090 #2 := false
 13090 #2 := false
 13091 decl f6 :: (-> S3 S2 S4)
 13091 decl f6 :: (-> S3 S2 S4)
 13092 decl f3 :: S2
 13092 decl f3 :: S2
 13093 #8 := f3
 13093 #8 := f3
 13094 decl f8 :: S3
 13094 decl f8 :: S3
 13277 #505 := [trans #511 #509]: #23
 13277 #505 := [trans #511 #509]: #23
 13278 #72 := (not #23)
 13278 #72 := (not #23)
 13279 #73 := [not-or-elim #70]: #72
 13279 #73 := [not-or-elim #70]: #72
 13280 [unit-resolution #73 #505]: false
 13280 [unit-resolution #73 #505]: false
 13281 unsat
 13281 unsat
 13282 25babfdee044def80821e354fcd8abca6147a0b0 80 0
 13282 0e78b14dde5af897ffb16aaeab92efe89c61b5d1 80 0
 13283 #2 := false
 13283 #2 := false
 13284 decl f6 :: (-> S2 S3 S1)
 13284 decl f6 :: (-> S2 S3 S1)
 13285 decl f5 :: S3
 13285 decl f5 :: S3
 13286 #9 := f5
 13286 #9 := f5
 13287 decl f4 :: S2
 13287 decl f4 :: S2
 13358 #92 := [monotonicity #89]: #91
 13358 #92 := [monotonicity #89]: #91
 13359 #96 := [trans #92 #94]: #95
 13359 #96 := [trans #92 #94]: #95
 13360 #75 := [not-or-elim #69]: #74
 13360 #75 := [not-or-elim #69]: #74
 13361 [mp #75 #96]: false
 13361 [mp #75 #96]: false
 13362 unsat
 13362 unsat
 13363 608cd0071a67598a13af0858c9e1341886caf8cc 128 0
 13363 df98f2515329e244654c3b6826b0db995088c21e 128 0
 13364 #2 := false
 13364 #2 := false
 13365 decl f3 :: (-> S2 S2)
 13365 decl f3 :: (-> S2 S2)
 13366 #15 := (:var 0 S2)
 13366 #15 := (:var 0 S2)
 13367 #16 := (f3 #15)
 13367 #16 := (f3 #15)
 13368 #577 := (pattern #16)
 13368 #577 := (pattern #16)
 13487 #576 := (not #578)
 13487 #576 := (not #578)
 13488 #566 := (or #576 #42)
 13488 #566 := (or #576 #42)
 13489 #224 := [quant-inst]: #566
 13489 #224 := [quant-inst]: #566
 13490 [unit-resolution #224 #575 #583]: false
 13490 [unit-resolution #224 #575 #583]: false
 13491 unsat
 13491 unsat
 13492 737f3f173e29756f346a0a821d7647d108111546 469 0
 13492 be52fda02d5daa6359d2f1d2bccf2f909cea5a49 469 0
 13493 #2 := false
 13493 #2 := false
 13494 decl f8 :: (-> S2 S4 S4)
 13494 decl f8 :: (-> S2 S4 S4)
 13495 decl f9 :: S4
 13495 decl f9 :: S4
 13496 #34 := f9
 13496 #34 := f9
 13497 decl f5 :: (-> int S2)
 13497 decl f5 :: (-> int S2)
 13957 #814 := [trans #809 #813]: #42
 13957 #814 := [trans #809 #813]: #42
 13958 #43 := (not #42)
 13958 #43 := (not #42)
 13959 #173 := [asserted]: #43
 13959 #173 := [asserted]: #43
 13960 [unit-resolution #173 #814]: false
 13960 [unit-resolution #173 #814]: false
 13961 unsat
 13961 unsat
 13962 5cfea173c08e120333c1dea606b9463cfcc6450a 38 0
 13962 ee30427d464b4fb3f94aa1806f026182963de849 38 0
 13963 #2 := false
 13963 #2 := false
 13964 decl f1 :: S1
 13964 decl f1 :: S1
 13965 #4 := f1
 13965 #4 := f1
 13966 decl f3 :: (-> S2 S1)
 13966 decl f3 :: (-> S2 S1)
 13967 #8 := (:var 0 S2)
 13967 #8 := (:var 0 S2)
 13996 #50 := [monotonicity #47]: #49
 13996 #50 := [monotonicity #47]: #49
 13997 #54 := [trans #50 #52]: #53
 13997 #54 := [trans #50 #52]: #53
 13998 #31 := [asserted]: #14
 13998 #31 := [asserted]: #14
 13999 [mp #31 #54]: false
 13999 [mp #31 #54]: false
 14000 unsat
 14000 unsat
 14001 9cf33fdca403c6c514f1cd0e17b6b0a250477095 366 0
 14001 bb6927e05e73f0d1fe00658a23b5a23277a4c6fa 366 0
 14002 #2 := false
 14002 #2 := false
 14003 decl f3 :: (-> int S2)
 14003 decl f3 :: (-> int S2)
 14004 #41 := 6::int
 14004 #41 := 6::int
 14005 #42 := (f3 6::int)
 14005 #42 := (f3 6::int)
 14006 decl f5 :: (-> S2 S2)
 14006 decl f5 :: (-> S2 S2)
 14363 #404 := [trans #411 #409]: #43
 14363 #404 := [trans #411 #409]: #43
 14364 #44 := (not #43)
 14364 #44 := (not #43)
 14365 #187 := [asserted]: #44
 14365 #187 := [asserted]: #44
 14366 [unit-resolution #187 #404]: false
 14366 [unit-resolution #187 #404]: false
 14367 unsat
 14367 unsat
 14368 f72e33edaef326a0ed844a14ae54b706945ff4d5 1271 0
 14368 760a08d06b818c4b3a173eacf882e5d9145febb7 1271 0
 14369 #2 := false
 14369 #2 := false
 14370 decl f6 :: (-> int int int)
 14370 decl f6 :: (-> int int int)
 14371 #12 := 2::int
 14371 #12 := 2::int
 14372 decl f14 :: int
 14372 decl f14 :: int
 14373 #84 := f14
 14373 #84 := f14
 15635 #646 := [def-axiom]: #645
 15635 #646 := [def-axiom]: #645
 15636 #638 := [unit-resolution #646 #1736]: #368
 15636 #638 := [unit-resolution #646 #1736]: #368
 15637 #615 := [unit-resolution #638 #1762]: #367
 15637 #615 := [unit-resolution #638 #1762]: #367
 15638 [unit-resolution #615 #1764]: false
 15638 [unit-resolution #615 #1764]: false
 15639 unsat
 15639 unsat
 15640 59b518b007738eb00dbca158af8db9e067af1dee 76 0
 15640 1739856e83271d60ba99b4dd0f8fab6bba11b19a 76 0
 15641 #2 := false
 15641 #2 := false
 15642 decl f3 :: (-> int S1)
 15642 decl f3 :: (-> int S1)
 15643 #12 := (:var 0 int)
 15643 #12 := (:var 0 int)
 15644 #13 := (f3 #12)
 15644 #13 := (f3 #12)
 15645 #1016 := (pattern #13)
 15645 #1016 := (pattern #13)
 15712 #603 := (not #1017)
 15712 #603 := (not #1017)
 15713 #688 := (or #603 #150)
 15713 #688 := (or #603 #150)
 15714 #689 := [quant-inst]: #688
 15714 #689 := [quant-inst]: #688
 15715 [unit-resolution #689 #158 #1022]: false
 15715 [unit-resolution #689 #158 #1022]: false
 15716 unsat
 15716 unsat
 15717 997a0c6c7b0815f9412f3484edb90c328a2f5296 478 0
 15717 e1c7435780cfee6dd8c9bac28159418631b73635 478 0
 15718 #2 := false
 15718 #2 := false
 15719 decl f7 :: (-> S4 S2)
 15719 decl f7 :: (-> S4 S2)
 15720 decl f8 :: (-> S1 S4)
 15720 decl f8 :: (-> S1 S4)
 15721 decl f1 :: S1
 15721 decl f1 :: S1
 15722 #4 := f1
 15722 #4 := f1