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Admin/Benchmarks/HOL-datatype/Verilog.thy
changeset 22875 9b21fa38a3cf
parent 16417 9bc16273c2d4
child 33695 bec342db1bf4 
--- a/Admin/Benchmarks/HOL-datatype/Verilog.thy	Tue May 08 17:40:22 2007 +0200
+++ b/Admin/Benchmarks/HOL-datatype/Verilog.thy	Tue May 08 17:41:35 2007 +0200
@@ -14,7 +14,7 @@
      | Source_textMeta string
 and
   Module_item
-     = declaration Declaration
+     = "declaration" Declaration
      | initial Statement
      | always Statement
      | assign Lvalue Expression
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