changeset 16417 | 9bc16273c2d4 |
parent 7373 | 776d888472aa |
child 22875 | 9b21fa38a3cf |
--- a/Admin/Benchmarks/HOL-datatype/Verilog.thy Fri Jun 17 11:35:35 2005 +0200 +++ b/Admin/Benchmarks/HOL-datatype/Verilog.thy Fri Jun 17 16:12:49 2005 +0200 @@ -2,7 +2,7 @@ ID: $Id$ *) -theory Verilog = Main: +theory Verilog imports Main begin (* ------------------------------------------------------------------------- *) (* Example from Daryl: a Verilog grammar. *)