# HG changeset patch
# User nipkow
# Date 755193910 -3600
# Node ID 831a9a7ab9f352c65b0f449630b428304c89362b
# Parent  6be0856cdf499193b4bed6d16d483776c615f550
added rep_tsig

diff -r 6be0856cdf49 -r 831a9a7ab9f3 src/Pure/type.ML
--- a/src/Pure/type.ML	Mon Dec 06 13:35:38 1993 +0100
+++ b/src/Pure/type.ML	Mon Dec 06 17:05:10 1993 +0100
@@ -21,8 +21,13 @@
 		   -> term * (indexname*typ)list
   val inst_term_tvars: type_sig * (indexname * typ)list -> term -> term
   val logical_type: type_sig -> string -> bool
-   val logical_types: type_sig -> string list
+  val logical_types: type_sig -> string list
   val merge: type_sig * type_sig -> type_sig
+  val rep_tsig: type_sig ->
+      {classes: class list, default: sort,
+       subclass: (class * class list) list,
+       args: (string * int) list,
+       coreg: (string * (class * sort list) list) list}
   val thaw_vars: typ -> typ
   val tsig0: type_sig
   val type_errors: type_sig * (typ->string) -> typ * string list -> string list
@@ -84,6 +89,7 @@
           represents the arity (ss)c
 *)
 
+fun rep_tsig (TySg comps) = comps;
 
 val tsig0 = TySg{classes = [],
 		 default = [],