# HG changeset patch # User paulson # Date 952614458 -3600 # Node ID c7772d3787c3657a5a6c1384a39ebe99de52c6b3 # Parent 5bf82327aa368c8db4ad5cbdb1430a131cbfd0d4 mod_less, div_less are now default simprules diff -r 5bf82327aa36 -r c7772d3787c3 src/HOL/Divides.ML --- a/src/HOL/Divides.ML Thu Mar 09 16:07:01 2000 +0100 +++ b/src/HOL/Divides.ML Thu Mar 09 16:07:38 2000 +0100 @@ -48,6 +48,7 @@ by (rtac (mod_eq RS wf_less_trans) 1); by (Asm_simp_tac 1); qed "mod_less"; +Addsimps [mod_less]; Goal "~ m < (n::nat) ==> m mod n = (m-n) mod n"; by (div_undefined_case_tac "n=0" 1); @@ -61,18 +62,18 @@ qed "le_mod_geq"; Goal "m mod (n::nat) = (if m m div n = Suc((m-n) div n)"; by (rtac (div_eq RS wf_less_trans) 1); @@ -148,7 +150,7 @@ qed "le_div_geq"; Goal "0 m div n = (if m n div n = 1"; -by (asm_simp_tac (simpset() addsimps [div_less, div_geq]) 1); +by (asm_simp_tac (simpset() addsimps [div_geq]) 1); qed "div_self"; @@ -205,12 +207,12 @@ Goal "0 div m = 0"; by (div_undefined_case_tac "m=0" 1); -by (asm_simp_tac (simpset() addsimps [div_less]) 1); +by (Asm_simp_tac 1); qed "div_0"; Goal "0 mod m = 0"; by (div_undefined_case_tac "m=0" 1); -by (asm_simp_tac (simpset() addsimps [mod_less]) 1); +by (Asm_simp_tac 1); qed "mod_0"; Addsimps [div_0, mod_0]; @@ -221,11 +223,11 @@ by (Clarify_tac 1); by (case_tac "n= k *) by (case_tac "m=k *) by (asm_simp_tac (simpset() addsimps [div_geq, diff_less, diff_le_mono]) 1); qed_spec_mp "div_le_mono"; @@ -237,7 +239,7 @@ by (res_inst_tac [("n","k")] less_induct 1); by (rename_tac "k" 1); by (case_tac "k