src/HOLCF/explicit_domains/Stream.ML
author paulson
Thu, 18 Jan 1996 10:38:29 +0100
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child 1461 6bcb44e4d6e5
permissions -rw-r--r--
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(*  
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    ID:         $Id$
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    Author: 	Franz Regensburger
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    Copyright   1993 Technische Universitaet Muenchen
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Lemmas for stream.thy
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*)
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open Stream;
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(* ------------------------------------------------------------------------*)
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(* The isomorphisms stream_rep_iso and stream_abs_iso are strict           *)
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(* ------------------------------------------------------------------------*)
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val stream_iso_strict= stream_rep_iso RS (stream_abs_iso RS 
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	(allI  RSN (2,allI RS iso_strict)));
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val stream_rews = [stream_iso_strict RS conjunct1,
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		stream_iso_strict RS conjunct2];
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(* ------------------------------------------------------------------------*)
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(* Properties of stream_copy                                               *)
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(* ------------------------------------------------------------------------*)
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fun prover defs thm =  prove_goalw Stream.thy defs thm
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(asm_simp_tac (!simpset addsimps 
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		(stream_rews @ [stream_abs_iso,stream_rep_iso])) 1)
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	]);
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val stream_copy = 
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	[
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	prover [stream_copy_def] "stream_copy`f`UU=UU",
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	prover [stream_copy_def,scons_def] 
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	"x~=UU ==> stream_copy`f`(scons`x`xs)= scons`x`(f`xs)"
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	];
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val stream_rews =  stream_copy @ stream_rews; 
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(* ------------------------------------------------------------------------*)
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(* Exhaustion and elimination for streams                                  *)
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(* ------------------------------------------------------------------------*)
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qed_goalw "Exh_stream" Stream.thy [scons_def]
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	"s = UU | (? x xs. x~=UU & s = scons`x`xs)"
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 (fn prems =>
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	[
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	(Simp_tac 1),
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	(rtac (stream_rep_iso RS subst) 1),
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	(res_inst_tac [("p","stream_rep`s")] sprodE 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1),
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	(Asm_simp_tac  1),
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	(res_inst_tac [("p","y")] liftE1 1),
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	(contr_tac 1),
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	(rtac disjI2 1),
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	(rtac exI 1),
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	(rtac exI 1),
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	(etac conjI 1),
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	(Asm_simp_tac  1)
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	]);
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qed_goal "streamE" Stream.thy 
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	"[| s=UU ==> Q; !!x xs.[|s=scons`x`xs;x~=UU|]==>Q|]==>Q"
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 (fn prems =>
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	[
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	(rtac (Exh_stream RS disjE) 1),
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	(eresolve_tac prems 1),
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	(etac exE 1),
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	(etac exE 1),
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	(resolve_tac prems 1),
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	(fast_tac HOL_cs 1),
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	(fast_tac HOL_cs 1)
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	]);
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(* ------------------------------------------------------------------------*)
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(* Properties of stream_when                                               *)
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(* ------------------------------------------------------------------------*)
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fun prover defs thm =  prove_goalw Stream.thy defs thm
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(asm_simp_tac (!simpset addsimps 
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		(stream_rews @ [stream_abs_iso,stream_rep_iso])) 1)
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	]);
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val stream_when = [
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	prover [stream_when_def] "stream_when`f`UU=UU",
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	prover [stream_when_def,scons_def] 
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		"x~=UU ==> stream_when`f`(scons`x`xs)= f`x`xs"
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	];
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val stream_rews = stream_when @ stream_rews;
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(* ------------------------------------------------------------------------*)
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(* Rewrites for  discriminators and  selectors                             *)
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(* ------------------------------------------------------------------------*)
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fun prover defs thm = prove_goalw Stream.thy defs thm
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 (fn prems =>
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	[
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	(simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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val stream_discsel = [
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	prover [is_scons_def] "is_scons`UU=UU",
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	prover [shd_def] "shd`UU=UU",
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	prover [stl_def] "stl`UU=UU"
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	];
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fun prover defs thm = prove_goalw Stream.thy defs thm
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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val stream_discsel = [
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prover [is_scons_def,shd_def,stl_def] "x~=UU ==> is_scons`(scons`x`xs)=TT",
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prover [is_scons_def,shd_def,stl_def] "x~=UU ==> shd`(scons`x`xs)=x",
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prover [is_scons_def,shd_def,stl_def] "x~=UU ==> stl`(scons`x`xs)=xs"
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	] @ stream_discsel;
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val stream_rews = stream_discsel @ stream_rews;
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(* ------------------------------------------------------------------------*)
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(* Definedness and strictness                                              *)
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(* ------------------------------------------------------------------------*)
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fun prover contr thm = prove_goal Stream.thy thm
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 (fn prems =>
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	[
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	(res_inst_tac [("P1",contr)] classical3 1),
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	(simp_tac (!simpset addsimps stream_rews) 1),
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	(dtac sym 1),
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	(Asm_simp_tac 1),
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	(simp_tac (!simpset addsimps (prems @ stream_rews)) 1)
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	]);
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val stream_constrdef = [
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	prover "is_scons`(UU::'a stream)~=UU" "x~=UU ==> scons`(x::'a)`xs~=UU"
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	]; 
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fun prover defs thm = prove_goalw Stream.thy defs thm
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 (fn prems =>
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	[
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	(simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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val stream_constrdef = [
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	prover [scons_def] "scons`UU`xs=UU"
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	] @ stream_constrdef;
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val stream_rews = stream_constrdef @ stream_rews;
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(* ------------------------------------------------------------------------*)
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(* Distinctness wrt. << and =                                              *)
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(* ------------------------------------------------------------------------*)
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(* ------------------------------------------------------------------------*)
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(* Invertibility                                                           *)
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(* ------------------------------------------------------------------------*)
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val stream_invert =
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	[
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prove_goal Stream.thy "[|x1~=UU; y1~=UU;\
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\ scons`x1`x2 << scons`y1`y2|] ==> x1<< y1 & x2 << y2"
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(rtac conjI 1),
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	(dres_inst_tac [("fo5","stream_when`(LAM x l.x)")] monofun_cfun_arg 1),
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	(etac box_less 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1),
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	(dres_inst_tac [("fo5","stream_when`(LAM x l.l)")] monofun_cfun_arg 1),
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	(etac box_less 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1)
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	])
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	];
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(* ------------------------------------------------------------------------*)
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(* Injectivity                                                             *)
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(* ------------------------------------------------------------------------*)
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val stream_inject = 
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	[
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prove_goal Stream.thy "[|x1~=UU; y1~=UU;\
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\ scons`x1`x2 = scons`y1`y2 |] ==> x1= y1 & x2 = y2"
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(rtac conjI 1),
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	(dres_inst_tac [("f","stream_when`(LAM x l.x)")] cfun_arg_cong 1),
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	(etac box_equals 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1),
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	(dres_inst_tac [("f","stream_when`(LAM x l.l)")] cfun_arg_cong 1),
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	(etac box_equals 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1),
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	(asm_simp_tac (!simpset addsimps stream_when) 1)
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	])
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	];
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(* ------------------------------------------------------------------------*)
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(* definedness for  discriminators and  selectors                          *)
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(* ------------------------------------------------------------------------*)
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fun prover thm = prove_goal Stream.thy thm
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(rtac streamE 1),
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	(contr_tac 1),
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	(REPEAT (asm_simp_tac (!simpset addsimps stream_discsel) 1))
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	]);
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val stream_discsel_def = 
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	[
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	prover "s~=UU ==> is_scons`s ~= UU", 
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	prover "s~=UU ==> shd`s ~=UU" 
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	];
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val stream_rews = stream_discsel_def @ stream_rews;
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(* ------------------------------------------------------------------------*)
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(* Properties stream_take                                                  *)
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(* ------------------------------------------------------------------------*)
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val stream_take =
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	[
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prove_goalw Stream.thy [stream_take_def] "stream_take n`UU = UU"
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 (fn prems =>
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	[
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	(res_inst_tac [("n","n")] natE 1),
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	(Asm_simp_tac 1),
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	(Asm_simp_tac 1),
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	(simp_tac (!simpset addsimps stream_rews) 1)
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	]),
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prove_goalw Stream.thy [stream_take_def] "stream_take 0`xs=UU"
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 (fn prems =>
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	[
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	(Asm_simp_tac 1)
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	])];
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fun prover thm = prove_goalw Stream.thy [stream_take_def] thm
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(Simp_tac 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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val stream_take = [
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prover 
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  "x~=UU ==> stream_take (Suc n)`(scons`x`xs) = scons`x`(stream_take n`xs)"
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	] @ stream_take;
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val stream_rews = stream_take @ stream_rews;
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(* ------------------------------------------------------------------------*)
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(* enhance the simplifier                                                  *)
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(* ------------------------------------------------------------------------*)
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qed_goal "stream_copy2" Stream.thy 
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     "stream_copy`f`(scons`x`xs) = scons`x`(f`xs)"
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 (fn prems =>
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	[
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	(res_inst_tac [("Q","x=UU")] classical2 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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qed_goal "shd2" Stream.thy "shd`(scons`x`xs) = x"
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 (fn prems =>
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	[
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	(res_inst_tac [("Q","x=UU")] classical2 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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qed_goal "stream_take2" Stream.thy 
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 "stream_take (Suc n)`(scons`x`xs) = scons`x`(stream_take n`xs)"
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 (fn prems =>
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	[
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	(res_inst_tac [("Q","x=UU")] classical2 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1),
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	(asm_simp_tac (!simpset addsimps stream_rews) 1)
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	]);
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val stream_rews = [stream_iso_strict RS conjunct1,
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		   stream_iso_strict RS conjunct2,
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                   hd stream_copy, stream_copy2]
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                  @ stream_when
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                  @ [hd stream_discsel,shd2] @ (tl (tl stream_discsel))  
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                  @ stream_constrdef
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                  @ stream_discsel_def
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                  @ [ stream_take2] @ (tl stream_take);
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(* ------------------------------------------------------------------------*)
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(* take lemma for streams                                                  *)
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(* ------------------------------------------------------------------------*)
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fun prover reach defs thm  = prove_goalw Stream.thy defs thm
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 (fn prems =>
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	[
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	(res_inst_tac [("t","s1")] (reach RS subst) 1),
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	(res_inst_tac [("t","s2")] (reach RS subst) 1),
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	(rtac (fix_def2 RS ssubst) 1),
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	(rtac (contlub_cfun_fun RS ssubst) 1),
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	(rtac is_chain_iterate 1),
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	(rtac (contlub_cfun_fun RS ssubst) 1),
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	(rtac is_chain_iterate 1),
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	(rtac lub_equal 1),
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	(rtac (is_chain_iterate RS ch2ch_fappL) 1),
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	(rtac (is_chain_iterate RS ch2ch_fappL) 1),
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	(rtac allI 1),
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	(resolve_tac prems 1)
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	]);
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val stream_take_lemma = prover stream_reach  [stream_take_def]
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	"(!!n.stream_take n`s1 = stream_take n`s2) ==> s1=s2";
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qed_goal "stream_reach2" Stream.thy  "lub(range(%i.stream_take i`s))=s"
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   334
 (fn prems =>
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	[
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	(res_inst_tac [("t","s")] (stream_reach RS subst) 1),
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	(rtac (fix_def2 RS ssubst) 1),
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	(rewrite_goals_tac [stream_take_def]),
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	(rtac (contlub_cfun_fun RS ssubst) 1),
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	(rtac is_chain_iterate 1),
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	(rtac refl 1)
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	]);
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(* ------------------------------------------------------------------------*)
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(* Co -induction for streams                                               *)
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(* ------------------------------------------------------------------------*)
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qed_goalw "stream_coind_lemma" Stream.thy [stream_bisim_def] 
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"stream_bisim R ==> ! p q. R p q --> stream_take n`p = stream_take n`q"
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 (fn prems =>
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	[
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	(cut_facts_tac prems 1),
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	(nat_ind_tac "n" 1),
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	(simp_tac (!simpset addsimps stream_rews) 1),
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diff changeset
   355
	(strip_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   356
	((etac allE 1) THEN (etac allE 1) THEN (etac (mp RS disjE) 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   357
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   358
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   359
	(etac exE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   360
	(etac exE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   361
	(etac exE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   362
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   363
	(REPEAT (etac conjE 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   364
	(rtac cfun_arg_cong 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   365
	(fast_tac HOL_cs 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   366
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   367
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   368
qed_goal "stream_coind" Stream.thy "[|stream_bisim R ;R p q|] ==> p = q"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   369
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   370
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   371
	(rtac stream_take_lemma 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   372
	(rtac (stream_coind_lemma RS spec RS spec RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   373
	(resolve_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   374
	(resolve_tac prems 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   375
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   376
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   377
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   378
(* structural induction for admissible predicates                          *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   379
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   380
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   381
qed_goal "stream_finite_ind" Stream.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   382
"[|P(UU);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   383
\  !! x s1.[|x~=UU;P(s1)|] ==> P(scons`x`s1)\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   384
\  |] ==> !s.P(stream_take n`s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   385
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   386
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   387
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   388
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   389
	(resolve_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   390
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   391
	(res_inst_tac [("s","s")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   392
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   393
	(resolve_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   394
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   395
	(resolve_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   396
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   397
	(etac spec 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   398
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   399
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   400
qed_goalw "stream_finite_ind2" Stream.thy  [stream_finite_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   401
"(!!n.P(stream_take n`s)) ==>  stream_finite(s) -->P(s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   402
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   403
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   404
	(strip_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   405
	(etac exE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   406
	(etac subst 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   407
	(resolve_tac prems 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   408
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   409
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   410
qed_goal "stream_finite_ind3" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   411
"[|P(UU);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   412
\  !! x s1.[|x~=UU;P(s1)|] ==> P(scons`x`s1)\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   413
\  |] ==> stream_finite(s) --> P(s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   414
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   415
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   416
	(rtac stream_finite_ind2 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   417
	(rtac (stream_finite_ind RS spec) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   418
	(REPEAT (resolve_tac prems 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   419
	(REPEAT (atac 1))
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   420
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   421
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   422
(* prove induction using definition of admissibility 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   423
   stream_reach rsp. stream_reach2 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   424
   and finite induction stream_finite_ind *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   425
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   426
qed_goal "stream_ind" Stream.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   427
"[|adm(P);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   428
\  P(UU);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   429
\  !! x s1.[|x~=UU;P(s1)|] ==> P(scons`x`s1)\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   430
\  |] ==> P(s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   431
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   432
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   433
	(rtac (stream_reach2 RS subst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   434
	(rtac (adm_def2 RS iffD1 RS spec RS mp RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   435
	(resolve_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   436
	(SELECT_GOAL (rewrite_goals_tac [stream_take_def]) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   437
	(rtac ch2ch_fappL 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   438
	(rtac is_chain_iterate 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   439
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   440
	(rtac (stream_finite_ind RS spec) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   441
	(REPEAT (resolve_tac prems 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   442
	(REPEAT (atac 1))
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   443
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   444
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   445
(* prove induction with usual LCF-Method using fixed point induction *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   446
qed_goal "stream_ind" Stream.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   447
"[|adm(P);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   448
\  P(UU);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   449
\  !! x s1.[|x~=UU;P(s1)|] ==> P(scons`x`s1)\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   450
\  |] ==> P(s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   451
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   452
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   453
	(rtac (stream_reach RS subst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   454
	(res_inst_tac [("x","s")] spec 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   455
	(rtac wfix_ind 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   456
	(rtac adm_impl_admw 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   457
	(REPEAT (resolve_tac adm_thms 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   458
	(rtac adm_subst 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   459
	(cont_tacR 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   460
	(resolve_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   461
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   462
	(rtac (rewrite_rule [stream_take_def] stream_finite_ind) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   463
	(REPEAT (resolve_tac prems 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   464
	(REPEAT (atac 1))
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   465
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   466
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   467
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   468
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   469
(* simplify use of Co-induction                                            *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   470
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   471
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   472
qed_goal "surjectiv_scons" Stream.thy "scons`(shd`s)`(stl`s)=s"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   473
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   474
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   475
	(res_inst_tac [("s","s")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   476
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   477
	(asm_simp_tac (!simpset addsimps stream_rews) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   478
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   479
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   480
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   481
qed_goalw "stream_coind_lemma2" Stream.thy [stream_bisim_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   482
"!s1 s2. R s1 s2 --> shd`s1 = shd`s2 & R (stl`s1) (stl`s2) ==> stream_bisim R"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   483
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   484
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   485
	(cut_facts_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   486
	(strip_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   487
	(etac allE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   488
	(etac allE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   489
	(dtac mp 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   490
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   491
	(etac conjE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   492
	(res_inst_tac [("Q","s1 = UU & s2 = UU")] classical2 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   493
	(rtac disjI1 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   494
	(fast_tac HOL_cs 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   495
	(rtac disjI2 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   496
	(rtac disjE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   497
	(etac (de_morgan2 RS ssubst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   498
	(res_inst_tac [("x","shd`s1")] exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   499
	(res_inst_tac [("x","stl`s1")] exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   500
	(res_inst_tac [("x","stl`s2")] exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   501
	(rtac conjI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   502
	(eresolve_tac stream_discsel_def 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   503
	(asm_simp_tac (!simpset addsimps stream_rews addsimps [surjectiv_scons]) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   504
	(eres_inst_tac [("s","shd`s1"),("t","shd`s2")] subst 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   505
	(simp_tac (!simpset addsimps stream_rews addsimps [surjectiv_scons]) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   506
	(res_inst_tac [("x","shd`s2")] exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   507
	(res_inst_tac [("x","stl`s1")] exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   508
	(res_inst_tac [("x","stl`s2")] exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   509
	(rtac conjI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   510
	(eresolve_tac stream_discsel_def 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   511
	(asm_simp_tac (!simpset addsimps stream_rews addsimps [surjectiv_scons]) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   512
	(res_inst_tac [("s","shd`s1"),("t","shd`s2")] ssubst 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   513
	(etac sym 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   514
	(simp_tac (!simpset addsimps stream_rews addsimps [surjectiv_scons]) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   515
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   516
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   517
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   518
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   519
(* theorems about finite and infinite streams                              *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   520
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   521
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   522
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   523
(* 2 lemmas about stream_finite                                            *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   524
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   525
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   526
qed_goalw "stream_finite_UU" Stream.thy [stream_finite_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   527
	 "stream_finite(UU)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   528
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   529
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   530
	(rtac exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   531
	(simp_tac (!simpset addsimps stream_rews) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   532
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   533
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   534
qed_goal "inf_stream_not_UU" Stream.thy  "~stream_finite(s)  ==> s ~= UU"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   535
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   536
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   537
	(cut_facts_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   538
	(etac swap 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   539
	(dtac notnotD 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   540
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   541
	(rtac stream_finite_UU 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   542
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   543
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   544
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   545
(* a lemma about shd                                                       *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   546
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   547
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   548
qed_goal "stream_shd_lemma1" Stream.thy "shd`s=UU --> s=UU"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   549
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   550
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   551
	(res_inst_tac [("s","s")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   552
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   553
	(hyp_subst_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   554
	(asm_simp_tac (!simpset addsimps stream_rews) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   555
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   556
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   557
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   558
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   559
(* lemmas about stream_take                                                *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   560
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   561
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   562
qed_goal "stream_take_lemma1" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   563
 "!x xs.x~=UU --> \
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   564
\  stream_take (Suc n)`(scons`x`xs) = scons`x`xs --> stream_take n`xs=xs"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   565
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   566
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   567
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   568
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   569
	(rtac impI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   570
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   571
	(strip_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   572
	(rtac ((hd stream_inject) RS conjunct2) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   573
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   574
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   575
	(atac 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   576
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   577
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   578
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   579
qed_goal "stream_take_lemma2" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   580
 "! s2. stream_take n`s2 = s2 --> stream_take (Suc n)`s2=s2"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   581
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   582
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   583
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   584
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   585
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   586
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   587
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   588
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   589
	(res_inst_tac [("s","s2")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   590
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   591
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   592
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   593
	(subgoal_tac "stream_take n1`xs = xs" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   594
	(rtac ((hd stream_inject) RS conjunct2) 2),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   595
	(atac 4),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   596
	(atac 2),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   597
	(atac 2),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   598
	(rtac cfun_arg_cong 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   599
	(fast_tac HOL_cs 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   600
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   601
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   602
qed_goal "stream_take_lemma3" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   603
 "!x xs.x~=UU --> \
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   604
\  stream_take n`(scons`x`xs) = scons`x`xs --> stream_take n`xs=xs"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   605
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   606
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   607
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   608
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   609
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   610
	(res_inst_tac [("P","scons`x`xs=UU")] notE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   611
	(eresolve_tac stream_constrdef 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   612
	(etac sym 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   613
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   614
	(rtac (stream_take_lemma2 RS spec RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   615
	(res_inst_tac [("x1.1","x")] ((hd stream_inject) RS conjunct2) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   616
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   617
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   618
	(etac (stream_take2 RS subst) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   619
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   620
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   621
qed_goal "stream_take_lemma4" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   622
 "!x xs.\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   623
\stream_take n`xs=xs --> stream_take (Suc n)`(scons`x`xs) = scons`x`xs"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   624
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   625
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   626
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   627
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   628
	(simp_tac (!simpset addsimps stream_rews) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   629
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   630
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   631
(* ---- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   632
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   633
qed_goal "stream_take_lemma5" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   634
"!s. stream_take n`s=s --> iterate n stl s=UU"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   635
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   636
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   637
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   638
	(Simp_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   639
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   640
	(strip_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   641
	(res_inst_tac [("s","s")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   642
	(hyp_subst_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   643
	(rtac (iterate_Suc2 RS ssubst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   644
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   645
	(rtac (iterate_Suc2 RS ssubst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   646
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   647
	(etac allE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   648
	(etac mp 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   649
	(hyp_subst_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   650
	(etac (stream_take_lemma1 RS spec RS spec RS mp RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   651
	(atac 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   652
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   653
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   654
qed_goal "stream_take_lemma6" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   655
"!s.iterate n stl s =UU --> stream_take n`s=s"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   656
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   657
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   658
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   659
	(Simp_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   660
	(strip_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   661
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   662
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   663
	(res_inst_tac [("s","s")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   664
	(hyp_subst_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   665
	(asm_simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   666
	(hyp_subst_tac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   667
	(rtac (iterate_Suc2 RS ssubst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   668
	(asm_simp_tac (!simpset addsimps stream_rews) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   669
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   670
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   671
qed_goal "stream_take_lemma7" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   672
"(iterate n stl s=UU) = (stream_take n`s=s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   673
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   674
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   675
	(rtac iffI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   676
	(etac (stream_take_lemma6 RS spec RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   677
	(etac (stream_take_lemma5 RS spec RS mp) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   678
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   679
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   680
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   681
qed_goal "stream_take_lemma8" Stream.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   682
"[|adm(P); !n. ? m. n < m & P (stream_take m`s)|] ==> P(s)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   683
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   684
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   685
	(cut_facts_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   686
	(rtac (stream_reach2 RS subst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   687
	(rtac adm_disj_lemma11 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   688
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   689
	(atac 2),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   690
	(rewrite_goals_tac [stream_take_def]),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   691
	(rtac ch2ch_fappL 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   692
	(rtac is_chain_iterate 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   693
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   694
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   695
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   696
(* lemmas stream_finite                                                    *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   697
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   698
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   699
qed_goalw "stream_finite_lemma1" Stream.thy [stream_finite_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   700
 "stream_finite(xs) ==> stream_finite(scons`x`xs)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   701
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   702
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   703
	(cut_facts_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   704
	(etac exE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   705
	(rtac exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   706
	(etac (stream_take_lemma4 RS spec RS spec RS mp) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   707
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   708
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   709
qed_goalw "stream_finite_lemma2" Stream.thy [stream_finite_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   710
 "[|x~=UU; stream_finite(scons`x`xs)|] ==> stream_finite(xs)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   711
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   712
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   713
	(cut_facts_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   714
	(etac exE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   715
	(rtac exI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   716
	(etac (stream_take_lemma3 RS spec RS spec RS mp RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   717
	(atac 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   718
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   719
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   720
qed_goal "stream_finite_lemma3" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   721
 "x~=UU ==> stream_finite(scons`x`xs) = stream_finite(xs)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   722
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   723
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   724
	(cut_facts_tac prems 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   725
	(rtac iffI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   726
	(etac stream_finite_lemma2 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   727
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   728
	(etac stream_finite_lemma1 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   729
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   730
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   731
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   732
qed_goalw "stream_finite_lemma5" Stream.thy [stream_finite_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   733
 "(!n. s1 << s2  --> stream_take n`s2 = s2 --> stream_finite(s1))\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   734
\=(s1 << s2  --> stream_finite(s2) --> stream_finite(s1))"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   735
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   736
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   737
	(rtac iffI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   738
	(fast_tac HOL_cs 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   739
	(fast_tac HOL_cs 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   740
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   741
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   742
qed_goal "stream_finite_lemma6" Stream.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   743
 "!s1 s2. s1 << s2  --> stream_take n`s2 = s2 --> stream_finite(s1)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   744
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   745
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   746
	(nat_ind_tac "n" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   747
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   748
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   749
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   750
	(dtac UU_I 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   751
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   752
	(rtac stream_finite_UU 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   753
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   754
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   755
	(res_inst_tac [("s","s1")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   756
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   757
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   758
	(rtac stream_finite_UU 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   759
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   760
	(res_inst_tac [("s","s2")] streamE 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   761
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   762
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   763
	(dtac UU_I 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   764
	(asm_simp_tac(!simpset addsimps (stream_rews @ [stream_finite_UU])) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   765
	(hyp_subst_tac  1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   766
	(simp_tac (!simpset addsimps stream_rews) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   767
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   768
	(rtac stream_finite_lemma1 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   769
	(subgoal_tac "xs << xsa" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   770
	(subgoal_tac "stream_take n1`xsa = xsa" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   771
	(fast_tac HOL_cs 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   772
	(res_inst_tac  [("x1.1","xa"),("y1.1","xa")] 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   773
                   ((hd stream_inject) RS conjunct2) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   774
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   775
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   776
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   777
	(res_inst_tac [("x1.1","x"),("y1.1","xa")]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   778
	 ((hd stream_invert) RS conjunct2) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   779
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   780
	(atac 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   781
	(atac 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   782
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   783
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   784
qed_goal "stream_finite_lemma7" Stream.thy 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   785
"s1 << s2  --> stream_finite(s2) --> stream_finite(s1)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   786
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   787
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   788
	(rtac (stream_finite_lemma5 RS iffD1) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   789
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   790
	(rtac (stream_finite_lemma6 RS spec RS spec) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   791
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   792
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   793
qed_goalw "stream_finite_lemma8" Stream.thy [stream_finite_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   794
"stream_finite(s) = (? n. iterate n stl s = UU)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   795
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   796
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   797
	(simp_tac (!simpset addsimps [stream_take_lemma7]) 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   798
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   799
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   800
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   801
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   802
(* admissibility of ~stream_finite                                         *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   803
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   804
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   805
qed_goalw "adm_not_stream_finite" Stream.thy [adm_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   806
 "adm(%s. ~ stream_finite(s))"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   807
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   808
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   809
	(strip_tac 1 ),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   810
	(res_inst_tac [("P1","!i. ~ stream_finite(Y(i))")] classical3 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   811
	(atac 2),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   812
	(subgoal_tac "!i.stream_finite(Y(i))" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   813
	(fast_tac HOL_cs 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   814
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   815
	(rtac (stream_finite_lemma7 RS mp RS mp) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   816
	(etac is_ub_thelub 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   817
	(atac 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   818
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   819
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   820
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   821
(* alternative prove for admissibility of ~stream_finite                   *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   822
(* show that stream_finite(s) = (? n. iterate n stl s = UU)                *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   823
(* and prove adm. of ~(? n. iterate n stl s = UU)                          *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   824
(* proof uses theorems stream_take_lemma5-7; stream_finite_lemma8          *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   825
(* ----------------------------------------------------------------------- *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   826
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   827
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   828
qed_goal "adm_not_stream_finite" Stream.thy "adm(%s. ~ stream_finite(s))"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   829
 (fn prems =>
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   830
	[
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   831
	(subgoal_tac "(!s.(~stream_finite(s))=(!n.iterate n stl s ~=UU))" 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   832
	(etac (adm_cong RS iffD2)1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   833
	(REPEAT(resolve_tac adm_thms 1)),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   834
	(rtac  cont_iterate2 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   835
	(rtac allI 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   836
	(rtac (stream_finite_lemma8 RS ssubst) 1),
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   837
	(fast_tac HOL_cs 1)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   838
	]);
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   839
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   840