| author | wenzelm |
| Wed, 29 Jun 2005 15:13:25 +0200 | |
| changeset 16595 | e64fb2cf50cb |
| parent 15408 | 6001135caa91 |
| child 17233 | 41eee2e7b465 |
| permissions | -rw-r--r-- |
| 3071 | 1 |
(* Title: HOLCF/IOA/meta_theory/RefMappings.ML |
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ID: $Id$ |
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Author: Olaf Müller |
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Refinement Mappings in HOLCF/IOA. |
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*) |
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(* ---------------------------------------------------------------------------- *) |
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section "transitions and moves"; |
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Goal "s -a--A-> t ==> ? ex. move A ex s a t"; |
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mueller
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by (res_inst_tac [("x","(a,t)>>nil")] exI 1);
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by (asm_full_simp_tac (simpset() addsimps [move_def]) 1); |
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qed"transition_is_ex"; |
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mueller
parents:
3275
diff
changeset
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Goal "(~a:ext A) & s=t ==> ? ex. move A ex s a t"; |
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3433
2de17c994071
added deadlock freedom, polished definitions and proofs
mueller
parents:
3275
diff
changeset
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by (res_inst_tac [("x","nil")] exI 1);
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by (asm_full_simp_tac (simpset() addsimps [move_def]) 1); |
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qed"nothing_is_ex"; |
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Goal "(s -a--A-> s') & (s' -a'--A-> s'') & (~a':ext A) \ |
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\ ==> ? ex. move A ex s a s''"; |
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3433
2de17c994071
added deadlock freedom, polished definitions and proofs
mueller
parents:
3275
diff
changeset
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by (res_inst_tac [("x","(a,s')>>(a',s'')>>nil")] exI 1);
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by (asm_full_simp_tac (simpset() addsimps [move_def]) 1); |
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qed"ei_transitions_are_ex"; |
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Goal "(s1 -a1--A-> s2) & (s2 -a2--A-> s3) & (s3 -a3--A-> s4) &\ |
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\ (~a2:ext A) & (~a3:ext A) ==> \ |
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\ ? ex. move A ex s1 a1 s4"; |
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3433
2de17c994071
added deadlock freedom, polished definitions and proofs
mueller
parents:
3275
diff
changeset
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by (res_inst_tac [("x","(a1,s2)>>(a2,s3)>>(a3,s4)>>nil")] exI 1);
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by (asm_full_simp_tac (simpset() addsimps [move_def]) 1); |
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qed"eii_transitions_are_ex"; |
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(* ---------------------------------------------------------------------------- *) |
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section "weak_ref_map and ref_map"; |
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Goalw [is_weak_ref_map_def,is_ref_map_def] |
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"[| ext C = ext A; \ |
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\ is_weak_ref_map f C A |] ==> is_ref_map f C A"; |
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by (safe_tac set_cs); |
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by (case_tac "a:ext A" 1); |
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by (rtac transition_is_ex 1); |
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by (Asm_simp_tac 1); |
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by (rtac nothing_is_ex 1); |
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by (Asm_simp_tac 1); |
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qed"weak_ref_map2ref_map"; |
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val prems = Goal "(P ==> Q-->R) ==> P&Q --> R"; |
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by (fast_tac (claset() addDs prems) 1); |
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qed "imp_conj_lemma"; |
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Delsplits [split_if]; Delcongs [if_weak_cong]; |
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Goal "[| is_weak_ref_map f C A |] \ |
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\ ==> (is_weak_ref_map f (rename C g) (rename A g))"; |
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by (asm_full_simp_tac (simpset() addsimps [is_weak_ref_map_def]) 1); |
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by (rtac conjI 1); |
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(* 1: start states *) |
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by (asm_full_simp_tac (simpset() addsimps [rename_def,rename_set_def,starts_of_def]) 1); |
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(* 2: reachable transitions *) |
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by (REPEAT (rtac allI 1)); |
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by (rtac imp_conj_lemma 1); |
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by (simp_tac (simpset() addsimps [rename_def,rename_set_def]) 1); |
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by (asm_full_simp_tac (simpset() addsimps [externals_def,asig_inputs_def, |
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asig_outputs_def,asig_of_def,trans_of_def]) 1); |
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by Safe_tac; |
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by (stac split_if 1); |
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by (rtac conjI 1); |
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by (rtac impI 1); |
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by (etac disjE 1); |
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by (etac exE 1); |
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by (etac conjE 1); |
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(* x is input *) |
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by (dtac sym 1); |
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by (dtac sym 1); |
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by (Asm_full_simp_tac 1); |
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by (REPEAT (hyp_subst_tac 1)); |
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by (ftac reachable_rename 1); |
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by (Asm_full_simp_tac 1); |
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(* x is output *) |
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by (etac exE 1); |
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by (etac conjE 1); |
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by (dtac sym 1); |
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by (dtac sym 1); |
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by (Asm_full_simp_tac 1); |
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by (REPEAT (hyp_subst_tac 1)); |
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by (ftac reachable_rename 1); |
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by (Asm_full_simp_tac 1); |
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(* x is internal *) |
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by (ftac reachable_rename 1); |
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by Auto_tac; |
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qed"rename_through_pmap"; |
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Addsplits [split_if]; Addcongs [if_weak_cong]; |
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