src/ZF/ArithSimp.ML
changeset 9907 473a6604da94
parent 9883 c1c8647af477
child 11386 cf8d81cf8034
equal deleted inserted replaced
9906:5c027cca6262 9907:473a6604da94
    73 by (etac rev_mp 1);
    73 by (etac rev_mp 1);
    74 by (res_inst_tac [("m","m"),("n","n")] diff_induct 1);
    74 by (res_inst_tac [("m","m"),("n","n")] diff_induct 1);
    75 by (ALLGOALS (asm_simp_tac (simpset() addsimps [diff_le_self])));
    75 by (ALLGOALS (asm_simp_tac (simpset() addsimps [diff_le_self])));
    76 qed "div_termination";
    76 qed "div_termination";
    77 
    77 
    78 val div_rls =   (*for mod and div*)
    78 bind_thms ("div_rls",   (*for mod and div*)
    79     nat_typechecks @
    79     nat_typechecks @
    80     [Ord_transrec_type, apply_funtype, div_termination RS ltD,
    80     [Ord_transrec_type, apply_funtype, div_termination RS ltD,
    81      nat_into_Ord, not_lt_iff_le RS iffD1];
    81      nat_into_Ord, not_lt_iff_le RS iffD1]);
    82 
    82 
    83 val div_ss = simpset() addsimps [div_termination RS ltD,
    83 val div_ss = simpset() addsimps [div_termination RS ltD,
    84 				 not_lt_iff_le RS iffD2];
    84 				 not_lt_iff_le RS iffD2];
    85 
    85 
    86 Goalw [raw_mod_def] "[| m:nat;  n:nat |] ==> raw_mod (m, n) : nat";
    86 Goalw [raw_mod_def] "[| m:nat;  n:nat |] ==> raw_mod (m, n) : nat";