1 (* |
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2 File: Memory.ML |
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3 ID: $Id$ |
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4 Author: Stephan Merz |
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5 Copyright: 1997 University of Munich |
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6 |
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7 RPC-Memory example: Memory specification (theorems and proofs) |
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8 *) |
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9 |
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10 val RM_action_defs = |
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11 [MInit_def, PInit_def, RdRequest_def, WrRequest_def, MemInv_def, |
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12 GoodRead_def, BadRead_def, ReadInner_def, Read_def, |
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13 GoodWrite_def, BadWrite_def, WriteInner_def, Write_def, |
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14 MemReturn_def, RNext_def]; |
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15 |
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16 val UM_action_defs = RM_action_defs @ [MemFail_def, UNext_def]; |
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17 |
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18 val RM_temp_defs = [RPSpec_def, MSpec_def, IRSpec_def]; |
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19 val UM_temp_defs = [UPSpec_def, MSpec_def, IUSpec_def]; |
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20 |
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21 val mem_css = (claset(), simpset()); |
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22 |
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23 (* -------------------- Proofs ---------------------------------------------- *) |
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24 |
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25 (* The reliable memory is an implementation of the unreliable one *) |
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26 Goal "|- IRSpec ch mm rs --> IUSpec ch mm rs"; |
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27 by (force_tac (temp_css addsimps2 ([UNext_def,UPSpec_def,IUSpec_def] @ RM_temp_defs) |
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28 addSEs2 [STL4E,squareE]) 1); |
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29 qed "ReliableImplementsUnReliable"; |
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30 |
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31 (* The memory spec implies the memory invariant *) |
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32 Goal "|- MSpec ch mm rs l --> [](MemInv mm l)"; |
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33 by (auto_inv_tac (simpset() addsimps RM_temp_defs @ RM_action_defs) 1); |
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34 qed "MemoryInvariant"; |
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35 |
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36 (* The invariant is trivial for non-locations *) |
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37 Goal "|- #l ~: #MemLoc --> [](MemInv mm l)"; |
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38 by (auto_tac (temp_css addsimps2 [MemInv_def] addSIs2 [necT])); |
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39 qed "NonMemLocInvariant"; |
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40 |
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41 Goal "|- (ALL l. #l : #MemLoc --> MSpec ch mm rs l) --> (ALL l. [](MemInv mm l))"; |
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42 by (step_tac temp_cs 1); |
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43 by (case_tac "l : MemLoc" 1); |
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44 by (auto_tac (temp_css addSEs2 [MemoryInvariant,NonMemLocInvariant])); |
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45 qed "MemoryInvariantAll"; |
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46 |
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47 (* The memory engages in an action for process p only if there is an |
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48 unanswered call from p. |
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49 We need this only for the reliable memory. |
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50 *) |
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51 |
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52 Goal "|- ~$(Calling ch p) --> ~ RNext ch mm rs p"; |
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53 by (auto_tac (mem_css addsimps2 (Return_def::RM_action_defs))); |
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54 qed "Memoryidle"; |
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55 |
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56 (* Enabledness conditions *) |
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57 |
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58 Goal "|- MemReturn ch rs p --> <MemReturn ch rs p>_(rtrner ch ! p, rs!p)"; |
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59 by (force_tac (mem_css addsimps2 [MemReturn_def,angle_def]) 1); |
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60 qed "MemReturn_change"; |
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61 |
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62 Goal "!!p. basevars (rtrner ch ! p, rs!p) ==> \ |
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63 \ |- Calling ch p & (rs!p ~= #NotAResult) \ |
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64 \ --> Enabled (<MemReturn ch rs p>_(rtrner ch ! p, rs!p))"; |
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65 by (action_simp_tac (simpset()) [MemReturn_change RSN (2,enabled_mono)] [] 1); |
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66 by (action_simp_tac (simpset() addsimps [MemReturn_def,Return_def,rtrner_def]) |
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67 [exI] [base_enabled,Pair_inject] 1); |
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68 qed "MemReturn_enabled"; |
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69 |
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70 Goal "!!p. basevars (rtrner ch ! p, rs!p) ==> \ |
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71 \ |- Calling ch p & (arg<ch!p> = #(read l)) --> Enabled (ReadInner ch mm rs p l)"; |
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72 by (case_tac "l : MemLoc" 1); |
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73 by (ALLGOALS |
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74 (force_tac (mem_css addsimps2 [ReadInner_def,GoodRead_def, |
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75 BadRead_def,RdRequest_def] |
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76 addSIs2 [exI] addSEs2 [base_enabled]))); |
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77 qed "ReadInner_enabled"; |
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78 |
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79 Goal "!!p. basevars (mm!l, rtrner ch ! p, rs!p) ==> \ |
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80 \ |- Calling ch p & (arg<ch!p> = #(write l v)) \ |
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81 \ --> Enabled (WriteInner ch mm rs p l v)"; |
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82 by (case_tac "l:MemLoc & v:MemVal" 1); |
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83 by (ALLGOALS |
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84 (force_tac (mem_css addsimps2 [WriteInner_def,GoodWrite_def, |
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85 BadWrite_def,WrRequest_def] |
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86 addSIs2 [exI] addSEs2 [base_enabled]))); |
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87 qed "WriteInner_enabled"; |
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88 |
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89 Goal "|- Read ch mm rs p & (!l. $(MemInv mm l)) --> (rs!p)` ~= #NotAResult"; |
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90 by (force_tac (mem_css addsimps2 |
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91 [Read_def,ReadInner_def,GoodRead_def,BadRead_def,MemInv_def]) 1); |
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92 qed "ReadResult"; |
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93 |
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94 Goal "|- Write ch mm rs p l --> (rs!p)` ~= #NotAResult"; |
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95 by (auto_tac (mem_css addsimps2 ([Write_def,WriteInner_def,GoodWrite_def,BadWrite_def]))); |
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96 qed "WriteResult"; |
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97 |
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98 Goal "|- (ALL l. $MemInv mm l) & MemReturn ch rs p \ |
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99 \ --> ~ Read ch mm rs p & (ALL l. ~ Write ch mm rs p l)"; |
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100 by (auto_tac (mem_css addsimps2 [MemReturn_def] addSDs2 [WriteResult, ReadResult])); |
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101 qed "ReturnNotReadWrite"; |
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102 |
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103 Goal "|- (rs!p = #NotAResult) & (!l. MemInv mm l) \ |
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104 \ & Enabled (Read ch mm rs p | (? l. Write ch mm rs p l)) \ |
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105 \ --> Enabled (<RNext ch mm rs p>_(rtrner ch ! p, rs!p))"; |
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106 by (force_tac (mem_css addsimps2 [RNext_def,angle_def] |
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107 addSEs2 [enabled_mono2] |
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108 addDs2 [ReadResult, WriteResult]) 1); |
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109 qed "RWRNext_enabled"; |
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110 |
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111 |
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112 (* Combine previous lemmas: the memory can make a visible step if there is an |
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113 outstanding call for which no result has been produced. |
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114 *) |
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115 Goal "!!p. !l. basevars (mm!l, rtrner ch!p, rs!p) ==> \ |
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116 \ |- (rs!p = #NotAResult) & Calling ch p & (!l. MemInv mm l) \ |
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117 \ --> Enabled (<RNext ch mm rs p>_(rtrner ch ! p, rs!p))"; |
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118 by (auto_tac (mem_css addsimps2 [enabled_disj] addSIs2 [RWRNext_enabled])); |
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119 by (case_tac "arg(ch w p)" 1); |
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120 by (action_simp_tac (simpset()addsimps[Read_def,enabled_ex]) |
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121 [ReadInner_enabled,exI] [] 1); |
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122 by (force_tac (mem_css addDs2 [base_pair]) 1); |
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123 by (etac contrapos_np 1); |
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124 by (action_simp_tac (simpset() addsimps [Write_def,enabled_ex]) |
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125 [WriteInner_enabled,exI] [] 1); |
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126 qed "RNext_enabled"; |
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