src/HOL/List.thy
changeset 63145 703edebd1d92
parent 63099 af0e964aad7b
child 63173 3413b1cf30cd
equal deleted inserted replaced
63143:ef72b104fa32 63145:703edebd1d92
  3004 by simp
  3004 by simp
  3005 
  3005 
  3006 lemma upt_conv_Cons: "i < j ==> [i..<j] = i # [Suc i..<j]"
  3006 lemma upt_conv_Cons: "i < j ==> [i..<j] = i # [Suc i..<j]"
  3007 by (simp add: upt_rec)
  3007 by (simp add: upt_rec)
  3008 
  3008 
  3009 lemma upt_conv_Cons_Cons: -- \<open>no precondition\<close>
  3009 lemma upt_conv_Cons_Cons: \<comment> \<open>no precondition\<close>
  3010   "m # n # ns = [m..<q] \<longleftrightarrow> n # ns = [Suc m..<q]"
  3010   "m # n # ns = [m..<q] \<longleftrightarrow> n # ns = [Suc m..<q]"
  3011 proof (cases "m < q")
  3011 proof (cases "m < q")
  3012   case False then show ?thesis by simp
  3012   case False then show ?thesis by simp
  3013 next
  3013 next
  3014   case True then show ?thesis by (simp add: upt_conv_Cons)
  3014   case True then show ?thesis by (simp add: upt_conv_Cons)