src/HOL/OrderedGroup.thy
changeset 19404 9bf2cdc9e8e8
parent 19233 77ca20b0ed77
child 19527 9b5c38e8e780
equal deleted inserted replaced
19403:5c15cd397a82 19404:9bf2cdc9e8e8
   852   by (simp add: le_def_join pprt_def join_aci)
   852   by (simp add: le_def_join pprt_def join_aci)
   853 
   853 
   854 lemma nprt_mono[simp]: "(a::_::lordered_ab_group) <= b \<Longrightarrow> nprt a <= nprt b"
   854 lemma nprt_mono[simp]: "(a::_::lordered_ab_group) <= b \<Longrightarrow> nprt a <= nprt b"
   855   by (simp add: le_def_meet nprt_def meet_aci)
   855   by (simp add: le_def_meet nprt_def meet_aci)
   856 
   856 
       
   857 lemma pprt_neg: "pprt (-x) = - nprt x"
       
   858   by (simp add: pprt_def nprt_def)
       
   859 
       
   860 lemma nprt_neg: "nprt (-x) = - pprt x"
       
   861   by (simp add: pprt_def nprt_def)
       
   862 
   857 lemma iff2imp: "(A=B) \<Longrightarrow> (A \<Longrightarrow> B)"
   863 lemma iff2imp: "(A=B) \<Longrightarrow> (A \<Longrightarrow> B)"
   858 by (simp)
   864 by (simp)
   859 
   865 
   860 lemma abs_of_nonneg [simp]: "0 \<le> a \<Longrightarrow> abs a = (a::'a::lordered_ab_group_abs)"
   866 lemma abs_of_nonneg [simp]: "0 \<le> a \<Longrightarrow> abs a = (a::'a::lordered_ab_group_abs)"
   861 by (simp add: iff2imp[OF zero_le_iff_zero_nprt] iff2imp[OF le_zero_iff_pprt_id] abs_prts)
   867 by (simp add: iff2imp[OF zero_le_iff_zero_nprt] iff2imp[OF le_zero_iff_pprt_id] abs_prts)
  1025 lemmas diff_eq_0_iff_eq = eq_iff_diff_eq_0 [symmetric]
  1031 lemmas diff_eq_0_iff_eq = eq_iff_diff_eq_0 [symmetric]
  1026 lemmas diff_le_0_iff_le = le_iff_diff_le_0 [symmetric]
  1032 lemmas diff_le_0_iff_le = le_iff_diff_le_0 [symmetric]
  1027 declare diff_less_0_iff_less [simp]
  1033 declare diff_less_0_iff_less [simp]
  1028 declare diff_eq_0_iff_eq [simp]
  1034 declare diff_eq_0_iff_eq [simp]
  1029 declare diff_le_0_iff_le [simp]
  1035 declare diff_le_0_iff_le [simp]
       
  1036 
       
  1037 
  1030 
  1038 
  1031 
  1039 
  1032 ML {*
  1040 ML {*
  1033 val add_zero_left = thm"add_0";
  1041 val add_zero_left = thm"add_0";
  1034 val add_zero_right = thm"add_0_right";
  1042 val add_zero_right = thm"add_0_right";