src/HOL/IMP/Examples.ML
changeset 11704 3c50a2cd6f00
parent 11701 3d51fbf81c17
child 11912 d1b341c3aabc
--- a/src/HOL/IMP/Examples.ML	Fri Oct 05 23:58:52 2001 +0200
+++ b/src/HOL/IMP/Examples.ML	Sat Oct 06 00:02:46 2001 +0200
@@ -34,7 +34,7 @@
 val step = resolve_tac evalc.intrs 1;
 val simp = Asm_simp_tac 1;
 Goalw [factorial_def] "a~=b ==> \
-\ <factorial a b, Mem(a:=# 3)>  -c-> Mem(b:=# 6,a:=Numeral0)";
+\ <factorial a b, Mem(a:=3)>  -c-> Mem(b:=6,a:=Numeral0)";
 by (ftac not_sym 1);
 by step;
 by  step;