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src/HOL/Word/Bits_Int.thy
changeset 71756 3d1f72d25fc3
parent 71181 8331063570d6
child 71826 f424e164d752 
--- a/src/HOL/Word/Bits_Int.thy	Thu Apr 16 08:09:28 2020 +0200
+++ b/src/HOL/Word/Bits_Int.thy	Thu Apr 16 08:09:29 2020 +0200
@@ -102,7 +102,7 @@
   "bin_last (numeral (Num.Bit1 w))"
   "\<not> bin_last (- numeral (Num.Bit0 w))"
   "bin_last (- numeral (Num.Bit1 w))"
-  by (simp_all add: bin_last_def zmod_zminus1_eq_if) (auto simp add: divmod_def)
+  by (simp_all add: bin_last_def zmod_zminus1_eq_if)
 
 lemma bin_rest_numeral_simps [simp]:
   "bin_rest 0 = 0"
@@ -113,7 +113,7 @@
   "bin_rest (numeral (Num.Bit1 w)) = numeral w"
   "bin_rest (- numeral (Num.Bit0 w)) = - numeral w"
   "bin_rest (- numeral (Num.Bit1 w)) = - numeral (w + Num.One)"
-  by (simp_all add: bin_rest_def zdiv_zminus1_eq_if) (auto simp add: divmod_def)
+  by (simp_all add: bin_rest_def zdiv_zminus1_eq_if)
 
 lemma less_Bits: "v BIT b < w BIT c \<longleftrightarrow> v < w \<or> v \<le> w \<and> \<not> b \<and> c"
   by (auto simp: Bit_def)
isabelle