src/HOL/Word/Bits_Int.thy
changeset 71989 bad75618fb82
parent 71986 76193dd4aec8
child 71991 8bff286878bf
--- a/src/HOL/Word/Bits_Int.thy	Thu Jul 02 08:49:04 2020 +0000
+++ b/src/HOL/Word/Bits_Int.thy	Thu Jul 02 12:10:58 2020 +0000
@@ -823,7 +823,6 @@
   apply clarsimp
   apply (drule bthrs)
   apply (simp (no_asm_use) add: Let_def split: prod.split_asm if_split_asm)
-  apply clarify
   apply (erule allE, erule impE, erule exI)
   apply (case_tac k)
    apply clarsimp