author | wenzelm |
Tue, 08 May 2007 17:41:35 +0200 | |
changeset 22875 | 9b21fa38a3cf |
parent 22874 | 58fcd4f9068a |
child 22876 | 2b4c831ceca7 |
--- a/Admin/Benchmarks/HOL-datatype/Verilog.thy Tue May 08 17:40:22 2007 +0200 +++ b/Admin/Benchmarks/HOL-datatype/Verilog.thy Tue May 08 17:41:35 2007 +0200 @@ -14,7 +14,7 @@ | Source_textMeta string and Module_item - = declaration Declaration + = "declaration" Declaration | initial Statement | always Statement | assign Lvalue Expression