src/HOLCF/explicit_domains/Dlist.ML
author paulson
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(*  Title:      HOLCF/Dlist.ML
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    Author:     Franz Regensburger
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    ID:         $ $
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    Copyright   1994 Technische Universitaet Muenchen
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Lemmas for dlist.thy
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*)
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open Dlist;
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(* ------------------------------------------------------------------------*)
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(* The isomorphisms dlist_rep_iso and dlist_abs_iso are strict             *)
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(* ------------------------------------------------------------------------*)
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val dlist_iso_strict= dlist_rep_iso RS (dlist_abs_iso RS 
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        (allI  RSN (2,allI RS iso_strict)));
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val dlist_rews = [dlist_iso_strict RS conjunct1,
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                dlist_iso_strict RS conjunct2];
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(* ------------------------------------------------------------------------*)
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(* Properties of dlist_copy                                                *)
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(* ------------------------------------------------------------------------*)
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val temp = prove_goalw Dlist.thy  [dlist_copy_def] "dlist_copy`f`UU=UU"
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 (fn prems =>
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        [
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        (asm_simp_tac (!simpset addsimps 
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                (dlist_rews @ [dlist_abs_iso,dlist_rep_iso])) 1)
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        ]);
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val dlist_copy = [temp];
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val temp = prove_goalw Dlist.thy  [dlist_copy_def,dnil_def] 
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    "dlist_copy`f`dnil=dnil"
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 (fn prems =>
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        [
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        (asm_simp_tac (!simpset addsimps 
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                (dlist_rews @ [dlist_abs_iso,dlist_rep_iso])) 1)
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        ]);
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val dlist_copy = temp :: dlist_copy;
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val temp = prove_goalw Dlist.thy  [dlist_copy_def,dcons_def] 
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        "xl~=UU ==> dlist_copy`f`(dcons`x`xl)= dcons`x`(f`xl)"
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 (fn prems =>
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        [
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        (cut_facts_tac prems 1),
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        (asm_simp_tac (!simpset addsimps 
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                (dlist_rews @ [dlist_abs_iso,dlist_rep_iso])) 1),
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        (case_tac "x=UU" 1),
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        (Asm_simp_tac  1),
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        (asm_simp_tac (!simpset addsimps [defined_spair]) 1)
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        ]);
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val dlist_copy = temp :: dlist_copy;
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val dlist_rews =  dlist_copy @ dlist_rews; 
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(* ------------------------------------------------------------------------*)
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(* Exhaustion and elimination for dlists                                   *)
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(* ------------------------------------------------------------------------*)
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qed_goalw "Exh_dlist" Dlist.thy [dcons_def,dnil_def]
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        "l = UU | l = dnil | (? x xl. x~=UU &xl~=UU & l = dcons`x`xl)"
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 (fn prems =>
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        [
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        (Simp_tac 1),
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        (rtac (dlist_rep_iso RS subst) 1),
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        (res_inst_tac [("p","dlist_rep`l")] ssumE 1),
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        (rtac disjI1 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (rtac disjI2 1),
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        (rtac disjI1 1),
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        (res_inst_tac [("p","x")] oneE 1),
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        (contr_tac 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (rtac disjI2 1),
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        (rtac disjI2 1),
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        (res_inst_tac [("p","y")] sprodE 1),
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        (contr_tac 1),
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        (rtac exI 1),
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        (rtac exI 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (fast_tac HOL_cs 1)
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        ]);
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qed_goal "dlistE" Dlist.thy 
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"[| l=UU ==> Q; l=dnil ==> Q;!!x xl.[|l=dcons`x`xl;x~=UU;xl~=UU|]==>Q|]==>Q"
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        [
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        (rtac (Exh_dlist RS disjE) 1),
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        (eresolve_tac prems 1),
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        (etac disjE 1),
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        (eresolve_tac prems 1),
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        (etac exE 1),
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        (etac exE 1),
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        (resolve_tac prems 1),
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        (fast_tac HOL_cs 1),
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        (fast_tac HOL_cs 1),
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        (fast_tac HOL_cs 1)
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        ]);
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(* ------------------------------------------------------------------------*)
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(* Properties of dlist_when                                                *)
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(* ------------------------------------------------------------------------*)
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val temp = prove_goalw  Dlist.thy  [dlist_when_def] "dlist_when`f1`f2`UU=UU"
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        [
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        (asm_simp_tac (!simpset addsimps [dlist_iso_strict]) 1)
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        ]);
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val dlist_when = [temp];
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val temp = prove_goalw  Dlist.thy [dlist_when_def,dnil_def]
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 "dlist_when`f1`f2`dnil= f1"
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        [
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        (asm_simp_tac (!simpset addsimps [dlist_abs_iso]) 1)
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        ]);
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val dlist_when = temp::dlist_when;
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val temp = prove_goalw  Dlist.thy [dlist_when_def,dcons_def]
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 "[|x~=UU;xl~=UU|] ==> dlist_when`f1`f2`(dcons`x`xl)= f2`x`xl"
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        [
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        (cut_facts_tac prems 1),
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        (asm_simp_tac (!simpset addsimps [dlist_abs_iso,defined_spair]) 1)
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        ]);
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val dlist_when = temp::dlist_when;
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val dlist_rews = dlist_when @ dlist_rews;
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(* ------------------------------------------------------------------------*)
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(* Rewrites for  discriminators and  selectors                             *)
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(* ------------------------------------------------------------------------*)
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fun prover defs thm = prove_goalw Dlist.thy defs thm
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 (fn prems =>
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        [
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        (simp_tac (!simpset addsimps dlist_rews) 1)
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        ]);
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val dlist_discsel = [
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        prover [is_dnil_def] "is_dnil`UU=UU",
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        prover [is_dcons_def] "is_dcons`UU=UU",
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        prover [dhd_def] "dhd`UU=UU",
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        prover [dtl_def] "dtl`UU=UU"
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        ];
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fun prover defs thm = prove_goalw Dlist.thy defs thm
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 (fn prems =>
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        [
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        (cut_facts_tac prems 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
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        ]);
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val dlist_discsel = [
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "is_dnil`dnil=TT",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "[|x~=UU;xl~=UU|] ==> is_dnil`(dcons`x`xl)=FF",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "is_dcons`dnil=FF",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "[|x~=UU;xl~=UU|] ==> is_dcons`(dcons`x`xl)=TT",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "dhd`dnil=UU",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "[|x~=UU;xl~=UU|] ==> dhd`(dcons`x`xl)=x",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "dtl`dnil=UU",
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prover [is_dnil_def,is_dcons_def,dhd_def,dtl_def]
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  "[|x~=UU;xl~=UU|] ==> dtl`(dcons`x`xl)=xl"] @ dlist_discsel;
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val dlist_rews = dlist_discsel @ dlist_rews;
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(* ------------------------------------------------------------------------*)
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(* Definedness and strictness                                              *)
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(* ------------------------------------------------------------------------*)
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fun prover contr thm = prove_goal Dlist.thy thm
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 (fn prems =>
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        [
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        (res_inst_tac [("P1",contr)] classical3 1),
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        (simp_tac (!simpset addsimps dlist_rews) 1),
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        (dtac sym 1),
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        (Asm_simp_tac  1),
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        (simp_tac (!simpset addsimps (prems @ dlist_rews)) 1)
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        ]);
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val dlist_constrdef = [
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prover "is_dnil`(UU::'a dlist) ~= UU" "dnil~=(UU::'a dlist)",
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prover "is_dcons`(UU::'a dlist) ~= UU" 
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        "[|x~=UU;xl~=UU|]==>dcons`(x::'a)`xl ~= UU"
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 ];
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fun prover defs thm = prove_goalw Dlist.thy defs thm
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 (fn prems =>
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        [
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        (simp_tac (!simpset addsimps dlist_rews) 1)
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        ]);
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val dlist_constrdef = [
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        prover [dcons_def] "dcons`UU`xl=UU",
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        prover [dcons_def] "dcons`x`UU=UU"
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        ] @ dlist_constrdef;
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val dlist_rews = dlist_constrdef @ dlist_rews;
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(* ------------------------------------------------------------------------*)
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(* Distinctness wrt. << and =                                              *)
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(* ------------------------------------------------------------------------*)
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val temp = prove_goal Dlist.thy  "~dnil << dcons`(x::'a)`xl"
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 (fn prems =>
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        [
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        (res_inst_tac [("P1","TT << FF")] classical3 1),
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        (resolve_tac dist_less_tr 1),
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        (dres_inst_tac [("fo5","is_dnil")] monofun_cfun_arg 1),
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        (etac box_less 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (case_tac "(x::'a)=UU" 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (case_tac "(xl ::'a dlist)=UU" 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
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        ]);
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val dlist_dist_less = [temp];
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val temp = prove_goal Dlist.thy  "[|x~=UU;xl~=UU|]==>~ dcons`x`xl << dnil"
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 (fn prems =>
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        [
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        (cut_facts_tac prems 1),
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        (res_inst_tac [("P1","TT << FF")] classical3 1),
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        (resolve_tac dist_less_tr 1),
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        (dres_inst_tac [("fo5","is_dcons")] monofun_cfun_arg 1),
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        (etac box_less 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
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        ]);
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val dlist_dist_less = temp::dlist_dist_less;
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val temp = prove_goal Dlist.thy  "dnil ~= dcons`x`xl"
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 (fn prems =>
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        [
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        (case_tac "x=UU" 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (case_tac "xl=UU" 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (res_inst_tac [("P1","TT = FF")] classical3 1),
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        (resolve_tac dist_eq_tr 1),
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        (dres_inst_tac [("f","is_dnil")] cfun_arg_cong 1),
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        (etac box_equals 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
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        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
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        ]);
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val dlist_dist_eq = [temp,temp RS not_sym];
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val dlist_rews = dlist_dist_less @ dlist_dist_eq @ dlist_rews;
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(* ------------------------------------------------------------------------*)
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(* Invertibility                                                           *)
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(* ------------------------------------------------------------------------*)
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val temp = prove_goal Dlist.thy "[|x1~=UU; y1~=UU;x2~=UU; y2~=UU;\
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\ dcons`x1`x2 << dcons`y1`y2 |] ==> x1<< y1 & x2 << y2"
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 (fn prems =>
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        [
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        (cut_facts_tac prems 1),
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        (rtac conjI 1),
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        (dres_inst_tac [("fo5","dlist_when`UU`(LAM x l.x)")] monofun_cfun_arg 1),
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        (etac box_less 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1),
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        (dres_inst_tac [("fo5","dlist_when`UU`(LAM x l.l)")] monofun_cfun_arg 1),
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        (etac box_less 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1)
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        ]);
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val dlist_invert =[temp];
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(* ------------------------------------------------------------------------*)
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(* Injectivity                                                             *)
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(* ------------------------------------------------------------------------*)
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val temp = prove_goal Dlist.thy "[|x1~=UU; y1~=UU;x2~=UU; y2~=UU;\
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\ dcons`x1`x2 = dcons`y1`y2 |] ==> x1= y1 & x2 = y2"
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 (fn prems =>
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        [
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        (cut_facts_tac prems 1),
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        (rtac conjI 1),
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        (dres_inst_tac [("f","dlist_when`UU`(LAM x l.x)")] cfun_arg_cong 1),
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        (etac box_equals 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1),
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        (dres_inst_tac [("f","dlist_when`UU`(LAM x l.l)")] cfun_arg_cong 1),
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        (etac box_equals 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1),
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        (asm_simp_tac (!simpset addsimps dlist_when) 1)
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        ]);
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val dlist_inject = [temp];
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(* ------------------------------------------------------------------------*)
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(* definedness for  discriminators and  selectors                          *)
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(* ------------------------------------------------------------------------*)
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fun prover thm = prove_goal Dlist.thy thm
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 (fn prems =>
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        [
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        (cut_facts_tac prems 1),
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        (rtac dlistE 1),
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        (contr_tac 1),
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        (REPEAT (asm_simp_tac (!simpset addsimps dlist_discsel) 1))
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        ]);
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val dlist_discsel_def = 
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        [
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        prover "l~=UU ==> is_dnil`l~=UU", 
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   335
        prover "l~=UU ==> is_dcons`l~=UU" 
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   336
        ];
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   337
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   338
val dlist_rews = dlist_discsel_def @ dlist_rews;
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   339
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   340
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   341
(* enhance the simplifier                                                  *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   342
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   343
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   344
qed_goal "dhd2" Dlist.thy "xl~=UU ==> dhd`(dcons`x`xl)=x"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   345
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   346
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   347
        (cut_facts_tac prems 1),
1675
36ba4da350c3 adapted several proofs
oheimb
parents: 1461
diff changeset
   348
        (case_tac "x=UU" 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   349
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   350
        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   351
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   352
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   353
qed_goal "dtl2" Dlist.thy "x~=UU ==> dtl`(dcons`x`xl)=xl"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   354
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   355
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   356
        (cut_facts_tac prems 1),
1675
36ba4da350c3 adapted several proofs
oheimb
parents: 1461
diff changeset
   357
        (case_tac "xl=UU" 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   358
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   359
        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   360
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   361
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   362
val dlist_rews = dhd2 :: dtl2 :: dlist_rews;
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   363
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   364
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   365
(* Properties dlist_take                                                   *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   366
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   367
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   368
val temp = prove_goalw Dlist.thy [dlist_take_def] "dlist_take n`UU=UU"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   369
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   370
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   371
        (res_inst_tac [("n","n")] natE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   372
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   373
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   374
        (simp_tac (!simpset addsimps dlist_rews) 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   375
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   376
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   377
val dlist_take = [temp];
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   378
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   379
val temp = prove_goalw Dlist.thy [dlist_take_def] "dlist_take 0`xs=UU"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   380
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   381
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   382
        (Asm_simp_tac 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   383
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   384
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   385
val dlist_take = temp::dlist_take;
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   386
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   387
val temp = prove_goalw Dlist.thy [dlist_take_def]
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   388
        "dlist_take (Suc n)`dnil=dnil"
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   389
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   390
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   391
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   392
        (simp_tac (!simpset addsimps dlist_rews) 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   393
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   394
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   395
val dlist_take = temp::dlist_take;
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   396
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   397
val temp = prove_goalw Dlist.thy [dlist_take_def]
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   398
  "dlist_take (Suc n)`(dcons`x`xl)= dcons`x`(dlist_take n`xl)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   399
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   400
        [
1675
36ba4da350c3 adapted several proofs
oheimb
parents: 1461
diff changeset
   401
        (case_tac "x=UU" 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   402
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   403
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
1675
36ba4da350c3 adapted several proofs
oheimb
parents: 1461
diff changeset
   404
        (case_tac "xl=UU" 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   405
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   406
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   407
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   408
        (res_inst_tac [("n","n")] natE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   409
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   410
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   411
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   412
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   413
        (Asm_simp_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   414
        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   415
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   416
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   417
val dlist_take = temp::dlist_take;
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   418
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   419
val dlist_rews = dlist_take @ dlist_rews;
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   420
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   421
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   422
(* take lemma for dlists                                                  *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   423
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   424
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   425
fun prover reach defs thm  = prove_goalw Dlist.thy defs thm
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   426
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   427
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   428
        (res_inst_tac [("t","l1")] (reach RS subst) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   429
        (res_inst_tac [("t","l2")] (reach RS subst) 1),
2033
639de962ded4 Ran expandshort; used stac instead of ssubst
paulson
parents: 1675
diff changeset
   430
        (stac fix_def2 1),
639de962ded4 Ran expandshort; used stac instead of ssubst
paulson
parents: 1675
diff changeset
   431
        (stac contlub_cfun_fun 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   432
        (rtac is_chain_iterate 1),
2033
639de962ded4 Ran expandshort; used stac instead of ssubst
paulson
parents: 1675
diff changeset
   433
        (stac contlub_cfun_fun 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   434
        (rtac is_chain_iterate 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   435
        (rtac lub_equal 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   436
        (rtac (is_chain_iterate RS ch2ch_fappL) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   437
        (rtac (is_chain_iterate RS ch2ch_fappL) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   438
        (rtac allI 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   439
        (resolve_tac prems 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   440
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   441
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   442
val dlist_take_lemma = prover dlist_reach  [dlist_take_def]
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   443
        "(!!n.dlist_take n`l1 = dlist_take n`l2) ==> l1=l2";
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   444
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   445
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   446
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   447
(* Co -induction for dlists                                               *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   448
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   449
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   450
qed_goalw "dlist_coind_lemma" Dlist.thy [dlist_bisim_def] 
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   451
"dlist_bisim R ==> ! p q. R p q --> dlist_take n`p = dlist_take n`q"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   452
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   453
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   454
        (cut_facts_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   455
        (nat_ind_tac "n" 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   456
        (simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   457
        (strip_tac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   458
        ((etac allE 1) THEN (etac allE 1) THEN (etac (mp RS disjE) 1)),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   459
        (atac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   460
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   461
        (etac disjE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   462
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   463
        (etac exE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   464
        (etac exE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   465
        (etac exE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   466
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   467
        (REPEAT (etac conjE 1)),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   468
        (rtac cfun_arg_cong 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   469
        (fast_tac HOL_cs 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   470
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   471
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   472
qed_goal "dlist_coind" Dlist.thy "[|dlist_bisim R ; R p q |] ==> p = q"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   473
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   474
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   475
        (rtac dlist_take_lemma 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   476
        (rtac (dlist_coind_lemma RS spec RS spec RS mp) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   477
        (resolve_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   478
        (resolve_tac prems 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   479
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   480
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   481
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   482
(* structural induction                                                    *)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   483
(* ------------------------------------------------------------------------*)
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   484
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   485
qed_goal "dlist_finite_ind" Dlist.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   486
"[|P(UU);P(dnil);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   487
\  !! x l1.[|x~=UU;l1~=UU;P(l1)|] ==> P(dcons`x`l1)\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   488
\  |] ==> !l.P(dlist_take n`l)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   489
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   490
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   491
        (nat_ind_tac "n" 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   492
        (simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   493
        (resolve_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   494
        (rtac allI 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   495
        (res_inst_tac [("l","l")] dlistE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   496
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   497
        (resolve_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   498
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   499
        (resolve_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   500
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
1675
36ba4da350c3 adapted several proofs
oheimb
parents: 1461
diff changeset
   501
        (case_tac "dlist_take n1`xl=UU" 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   502
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   503
        (resolve_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   504
        (resolve_tac prems 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   505
        (atac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   506
        (atac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   507
        (etac spec 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   508
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   509
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   510
qed_goal "dlist_all_finite_lemma1" Dlist.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   511
"!l.dlist_take n`l=UU |dlist_take n`l=l"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   512
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   513
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   514
        (nat_ind_tac "n" 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   515
        (simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   516
        (rtac allI 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   517
        (res_inst_tac [("l","l")] dlistE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   518
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   519
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   520
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   521
        (eres_inst_tac [("x","xl")] allE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   522
        (etac disjE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   523
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   524
        (asm_simp_tac (!simpset addsimps dlist_rews) 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   525
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   526
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   527
qed_goal "dlist_all_finite_lemma2" Dlist.thy "? n.dlist_take n`l=l"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   528
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   529
        [
1675
36ba4da350c3 adapted several proofs
oheimb
parents: 1461
diff changeset
   530
        (case_tac "l=UU" 1),
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   531
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   532
        (subgoal_tac "(!n.dlist_take n`l=UU) |(? n.dlist_take n`l = l)" 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   533
        (etac disjE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   534
        (eres_inst_tac [("P","l=UU")] notE 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   535
        (rtac dlist_take_lemma 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   536
        (asm_simp_tac (!simpset addsimps dlist_rews) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   537
        (atac 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   538
        (subgoal_tac "!n.!l.dlist_take n`l=UU |dlist_take n`l=l" 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   539
        (fast_tac HOL_cs 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   540
        (rtac allI 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   541
        (rtac dlist_all_finite_lemma1 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   542
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   543
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   544
qed_goalw "dlist_all_finite" Dlist.thy [dlist_finite_def] "dlist_finite(l)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   545
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   546
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   547
        (rtac  dlist_all_finite_lemma2 1)
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   548
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   549
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   550
qed_goal "dlist_ind" Dlist.thy
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   551
"[|P(UU);P(dnil);\
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   552
\  !! x l1.[|x~=UU;l1~=UU;P(l1)|] ==> P(dcons`x`l1)|] ==> P(l)"
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   553
 (fn prems =>
1461
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   554
        [
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   555
        (rtac (dlist_all_finite_lemma2 RS exE) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   556
        (etac subst 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   557
        (rtac (dlist_finite_ind RS spec) 1),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   558
        (REPEAT (resolve_tac prems 1)),
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   559
        (REPEAT (atac 1))
6bcb44e4d6e5 expanded tabs
clasohm
parents: 1274
diff changeset
   560
        ]);
1274
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   561
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   562
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   563
ea0668a1c0ba added 8bit pragmas
regensbu
parents:
diff changeset
   564