author | wenzelm |
Fri, 05 Oct 2001 23:58:52 +0200 | |
changeset 11703 | 6e5de8d4290a |
parent 10231 | 178a272bceeb |
child 17309 | c43ed29bd197 |
permissions | -rw-r--r-- |
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(* |
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File: Memory.ML |
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Author: Stephan Merz |
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Copyright: 1997 University of Munich |
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RPC-Memory example: Memory specification (theorems and proofs) |
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*) |
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val RM_action_defs = |
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[MInit_def, PInit_def, RdRequest_def, WrRequest_def, MemInv_def, |
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GoodRead_def, BadRead_def, ReadInner_def, Read_def, |
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GoodWrite_def, BadWrite_def, WriteInner_def, Write_def, |
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MemReturn_def, RNext_def]; |
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val UM_action_defs = RM_action_defs @ [MemFail_def, UNext_def]; |
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val RM_temp_defs = [RPSpec_def, MSpec_def, IRSpec_def]; |
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val UM_temp_defs = [UPSpec_def, MSpec_def, IUSpec_def]; |
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||
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val mem_css = (claset(), simpset()); |
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(* -------------------- Proofs ---------------------------------------------- *) |
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(* The reliable memory is an implementation of the unreliable one *) |
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Goal "|- IRSpec ch mm rs --> IUSpec ch mm rs"; |
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by (force_tac (temp_css addsimps2 ([UNext_def,UPSpec_def,IUSpec_def] @ RM_temp_defs) |
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addSEs2 [STL4E,squareE]) 1); |
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qed "ReliableImplementsUnReliable"; |
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(* The memory spec implies the memory invariant *) |
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Goal "|- MSpec ch mm rs l --> [](MemInv mm l)"; |
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by (auto_inv_tac (simpset() addsimps RM_temp_defs @ RM_action_defs) 1); |
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qed "MemoryInvariant"; |
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(* The invariant is trivial for non-locations *) |
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Goal "|- #l ~: #MemLoc --> [](MemInv mm l)"; |
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by (auto_tac (temp_css addsimps2 [MemInv_def] addSIs2 [necT])); |
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qed "NonMemLocInvariant"; |
3807 | 39 |
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Goal "|- (ALL l. #l : #MemLoc --> MSpec ch mm rs l) --> (ALL l. [](MemInv mm l))"; |
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by (step_tac temp_cs 1); |
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by (case_tac "l : MemLoc" 1); |
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by (auto_tac (temp_css addSEs2 [MemoryInvariant,NonMemLocInvariant])); |
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qed "MemoryInvariantAll"; |
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(* The memory engages in an action for process p only if there is an |
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unanswered call from p. |
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We need this only for the reliable memory. |
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*) |
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||
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Goal "|- ~$(Calling ch p) --> ~ RNext ch mm rs p"; |
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by (auto_tac (mem_css addsimps2 (Return_def::RM_action_defs))); |
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qed "Memoryidle"; |
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(* Enabledness conditions *) |
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Goal "|- MemReturn ch rs p --> <MemReturn ch rs p>_(rtrner ch ! p, rs!p)"; |
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by (force_tac (mem_css addsimps2 [MemReturn_def,angle_def]) 1); |
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qed "MemReturn_change"; |
3807 | 60 |
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Goal "!!p. basevars (rtrner ch ! p, rs!p) ==> \ |
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\ |- Calling ch p & (rs!p ~= #NotAResult) \ |
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\ --> Enabled (<MemReturn ch rs p>_(rtrner ch ! p, rs!p))"; |
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by (action_simp_tac (simpset()) [MemReturn_change RSN (2,enabled_mono)] [] 1); |
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by (action_simp_tac (simpset() addsimps [MemReturn_def,Return_def,rtrner_def]) |
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[exI] [base_enabled,Pair_inject] 1); |
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qed "MemReturn_enabled"; |
3807 | 68 |
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Goal "!!p. basevars (rtrner ch ! p, rs!p) ==> \ |
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\ |- Calling ch p & (arg<ch!p> = #(read l)) --> Enabled (ReadInner ch mm rs p l)"; |
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by (case_tac "l : MemLoc" 1); |
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by (ALLGOALS |
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(force_tac (mem_css addsimps2 [ReadInner_def,GoodRead_def, |
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BadRead_def,RdRequest_def] |
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addSIs2 [exI] addSEs2 [base_enabled]))); |
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qed "ReadInner_enabled"; |
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Goal "!!p. basevars (mm!l, rtrner ch ! p, rs!p) ==> \ |
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\ |- Calling ch p & (arg<ch!p> = #(write l v)) \ |
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\ --> Enabled (WriteInner ch mm rs p l v)"; |
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by (case_tac "l:MemLoc & v:MemVal" 1); |
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by (ALLGOALS |
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(force_tac (mem_css addsimps2 [WriteInner_def,GoodWrite_def, |
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BadWrite_def,WrRequest_def] |
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addSIs2 [exI] addSEs2 [base_enabled]))); |
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qed "WriteInner_enabled"; |
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Goal "|- Read ch mm rs p & (!l. $(MemInv mm l)) --> (rs!p)` ~= #NotAResult"; |
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by (force_tac (mem_css addsimps2 |
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[Read_def,ReadInner_def,GoodRead_def,BadRead_def,MemInv_def]) 1); |
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qed "ReadResult"; |
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Goal "|- Write ch mm rs p l --> (rs!p)` ~= #NotAResult"; |
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by (auto_tac (mem_css addsimps2 ([Write_def,WriteInner_def,GoodWrite_def,BadWrite_def]))); |
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qed "WriteResult"; |
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Goal "|- (ALL l. $MemInv mm l) & MemReturn ch rs p \ |
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\ --> ~ Read ch mm rs p & (ALL l. ~ Write ch mm rs p l)"; |
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by (auto_tac (mem_css addsimps2 [MemReturn_def] addSDs2 [WriteResult, ReadResult])); |
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qed "ReturnNotReadWrite"; |
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Goal "|- (rs!p = #NotAResult) & (!l. MemInv mm l) \ |
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\ & Enabled (Read ch mm rs p | (? l. Write ch mm rs p l)) \ |
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\ --> Enabled (<RNext ch mm rs p>_(rtrner ch ! p, rs!p))"; |
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by (force_tac (mem_css addsimps2 [RNext_def,angle_def] |
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addSEs2 [enabled_mono2] |
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addDs2 [ReadResult, WriteResult]) 1); |
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qed "RWRNext_enabled"; |
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(* Combine previous lemmas: the memory can make a visible step if there is an |
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outstanding call for which no result has been produced. |
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*) |
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Goal "!!p. !l. basevars (mm!l, rtrner ch!p, rs!p) ==> \ |
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\ |- (rs!p = #NotAResult) & Calling ch p & (!l. MemInv mm l) \ |
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\ --> Enabled (<RNext ch mm rs p>_(rtrner ch ! p, rs!p))"; |
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by (auto_tac (mem_css addsimps2 [enabled_disj] addSIs2 [RWRNext_enabled])); |
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by (case_tac "arg(ch w p)" 1); |
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by (action_simp_tac (simpset()addsimps[Read_def,enabled_ex]) |
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[ReadInner_enabled,exI] [] 1); |
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by (force_tac (mem_css addDs2 [base_pair]) 1); |
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by (etac contrapos_np 1); |
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by (action_simp_tac (simpset() addsimps [Write_def,enabled_ex]) |
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[WriteInner_enabled,exI] [] 1); |
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qed "RNext_enabled"; |