src/HOL/MetisExamples/Message.thy
changeset 32705 04ce6bb14d85
parent 32685 29e4e567b5f4
child 32864 a226f29d4bdc
equal deleted inserted replaced
32682:304a47739407 32705:04ce6bb14d85
     1 (*  Title:      HOL/MetisTest/Message.thy
     1 (*  Title:      HOL/MetisTest/Message.thy
     2     ID:         $Id$
       
     3     Author:     Lawrence C Paulson, Cambridge University Computer Laboratory
     2     Author:     Lawrence C Paulson, Cambridge University Computer Laboratory
     4 
     3 
     5 Testing the metis method
     4 Testing the metis method
     6 *)
     5 *)
     7 
     6 
   709 ML{*AtpWrapper.problem_name := "Message__analz_synth"*}
   708 ML{*AtpWrapper.problem_name := "Message__analz_synth"*}
   710 lemma analz_synth [simp]: "analz (synth H) = analz H \<union> synth H"
   709 lemma analz_synth [simp]: "analz (synth H) = analz H \<union> synth H"
   711 proof (neg_clausify)
   710 proof (neg_clausify)
   712 assume 0: "analz (synth H) \<noteq> analz H \<union> synth H"
   711 assume 0: "analz (synth H) \<noteq> analz H \<union> synth H"
   713 have 1: "\<And>X1 X3. sup (analz (sup X3 X1)) (synth X3) = analz (sup (synth X3) X1)"
   712 have 1: "\<And>X1 X3. sup (analz (sup X3 X1)) (synth X3) = analz (sup (synth X3) X1)"
   714   by (metis analz_synth_Un sup_set_eq sup_set_eq sup_set_eq)
   713   by (metis analz_synth_Un)
   715 have 2: "sup (analz H) (synth H) \<noteq> analz (synth H)"
   714 have 2: "sup (analz H) (synth H) \<noteq> analz (synth H)"
   716   by (metis 0 sup_set_eq)
   715   by (metis 0)
   717 have 3: "\<And>X1 X3. sup (synth X3) (analz (sup X3 X1)) = analz (sup (synth X3) X1)"
   716 have 3: "\<And>X1 X3. sup (synth X3) (analz (sup X3 X1)) = analz (sup (synth X3) X1)"
   718   by (metis 1 Un_commute sup_set_eq sup_set_eq)
   717   by (metis 1 Un_commute)
   719 have 4: "\<And>X3. sup (synth X3) (analz X3) = analz (sup (synth X3) {})"
   718 have 4: "\<And>X3. sup (synth X3) (analz X3) = analz (sup (synth X3) {})"
   720   by (metis 3 Un_empty_right sup_set_eq)
   719   by (metis 3 Un_empty_right)
   721 have 5: "\<And>X3. sup (synth X3) (analz X3) = analz (synth X3)"
   720 have 5: "\<And>X3. sup (synth X3) (analz X3) = analz (synth X3)"
   722   by (metis 4 Un_empty_right sup_set_eq)
   721   by (metis 4 Un_empty_right)
   723 have 6: "\<And>X3. sup (analz X3) (synth X3) = analz (synth X3)"
   722 have 6: "\<And>X3. sup (analz X3) (synth X3) = analz (synth X3)"
   724   by (metis 5 Un_commute sup_set_eq sup_set_eq)
   723   by (metis 5 Un_commute)
   725 show "False"
   724 show "False"
   726   by (metis 2 6)
   725   by (metis 2 6)
   727 qed
   726 qed
   728 
   727 
   729 
   728