changeset 44639 | 83dc04ccabd5 |
parent 38798 | 89f273ab1d42 |
--- a/Admin/Benchmarks/HOL-datatype/ROOT.ML Thu Sep 01 14:35:51 2011 +0200 +++ b/Admin/Benchmarks/HOL-datatype/ROOT.ML Thu Sep 01 16:46:07 2011 +0200 @@ -5,7 +5,7 @@ val tests = ["Brackin", "Instructions", "SML", "Verilog"]; -timing := true; +Toplevel.timing := true; warning "\nset quick_and_dirty\n"; quick_and_dirty := true; use_thys tests;